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    Searched refs:CLK_UART0_INTERNAL_DIV (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
pistachio-clk.h 68 #define CLK_UART0_INTERNAL_DIV 76
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/
pistachio.dtsi 259 assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,

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