| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 507 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
513 CONCAT_VECTORS,
560 /// VEC1/VEC2 from CONCAT_VECTORS(VEC1, VEC2), based on the IMM in two ways.
563 /// from CONCAT_VECTORS(VEC1, VEC2). If IMM is negative it represents a count
566 /// RESULT[i] = CONCAT_VECTORS(VEC1,VEC2)[VEC1.ElementCount - ABS(IMM) + i]
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 120 setOperationAction(ISD::CONCAT_VECTORS, T, Custom);
154 setOperationAction(ISD::CONCAT_VECTORS, T, Custom);
224 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom);
366 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)),
1051 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1});
1052 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV});
1098 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1});
1099 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV});
1244 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
1319 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy
[all...] |
| HexagonISelLowering.cpp | 1489 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1649 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE,
1699 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
2720 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats);
3137 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
|
| HexagonISelDAGToDAGHVX.cpp | 1477 // XXX CONCAT_VECTORS is legal for HVX vectors. Legalizing (lowering)
1481 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1});
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 622 case ISD::CONCAT_VECTORS:
921 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
1234 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
1247 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
1250 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
1558 ISD::CONCAT_VECTORS, dl, OtherVT,
2159 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
2285 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
2359 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
2503 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi)
[all...] |
| DAGCombiner.cpp | 1713 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
9577 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
9578 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
9587 // concat_vectors we have as arguments to vselect.
9618 ISD::CONCAT_VECTORS, DL, VT,
10071 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
10072 N2.getOpcode() == ISD::CONCAT_VECTORS &&
10430 // (v8i32 (concat_vectors (v4i32 (sextload x)),
10436 // (v8i32 (concat_vectors (v4i32 (sextload x)),
10499 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads)
[all...] |
| SelectionDAGDumper.cpp | 286 case ISD::CONCAT_VECTORS: return "concat_vectors";
|
| LegalizeDAG.cpp | 1428 Node->getOpcode() == ISD::CONCAT_VECTORS) &&
2987 case ISD::CONCAT_VECTORS:
4773 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4788 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4895 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4910 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
|
| SelectionDAG.cpp | 2854 case ISD::CONCAT_VECTORS: {
4105 case ISD::CONCAT_VECTORS: {
4801 case ISD::CONCAT_VECTORS:
5142 // We can't create a scalar CONCAT_VECTORS so skip it. It will break
5145 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS)
5518 case ISD::CONCAT_VECTORS: {
5748 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
5753 N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) {
5866 if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0 &&
6003 case ISD::CONCAT_VECTORS:
[all...] |
| SelectionDAGBuilder.cpp | 380 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
390 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
3606 // a CONCAT_VECTORS operation.
3617 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3635 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3636 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
5484 case ISD::CONCAT_VECTORS:
|
| LegalizeIntegerTypes.cpp | 114 case ISD::CONCAT_VECTORS:
1255 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1491 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
|
| TargetLowering.cpp | 1109 case ISD::CONCAT_VECTORS: {
2555 case ISD::CONCAT_VECTORS: {
8742 // Store the lo part of CONCAT_VECTORS(V1, V2)
8744 // Store the hi part of CONCAT_VECTORS(V1, V2)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 1423 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1498 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1724 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1876 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
2009 setTargetDAGCombine(ISD::CONCAT_VECTORS);
2990 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
5995 // either by ISD::CONCAT_VECTORS or a ISD::INSERT_SUBVECTOR series.
6000 if (N->getOpcode() == ISD::CONCAT_VECTORS) {
6069 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
6096 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 322 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
323 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
324 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
325 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
326 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom);
327 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
328 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
329 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1240 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1562 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad)
[all...] |
| SIISelLowering.cpp | 261 case ISD::CONCAT_VECTORS:
584 case ISD::CONCAT_VECTORS:
4423 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4447 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4471 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
5525 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
5528 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
5531 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
5563 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
6384 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 158 setTargetDAGCombine(ISD::CONCAT_VECTORS);
2195 assert(N->getOpcode() == ISD::CONCAT_VECTORS);
2199 // (concat_vectors (v2i32 (fp_to_{s,u}int_sat $x, 32)), (v2i32 (splat 0)))
2249 case ISD::CONCAT_VECTORS:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 896 setTargetDAGCombine(ISD::CONCAT_VECTORS);
1175 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1217 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1253 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1387 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
4354 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16,
4552 case ISD::CONCAT_VECTORS:
8289 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
8765 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
8904 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
442 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
7680 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper);
7818 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
8426 // Also check for these shuffles through CONCAT_VECTORS: we canonicalize
8441 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
8459 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
8651 "Unexpected custom CONCAT_VECTORS lowering");
8653 "CONCAT_VECTORS lowering only supported for MVE");
8697 // The only time a CONCAT_VECTORS operation can have legal types is whe
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 741 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 520 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
584 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
638 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1725 // Peek through CONCAT_VECTORS as VectorCombine can concat a vector
1729 if (V.getOpcode() == ISD::CONCAT_VECTORS) {
2316 case ISD::CONCAT_VECTORS: {
2317 // Split CONCAT_VECTORS into a series of INSERT_SUBVECTOR nodes. This is
4004 // FIXME: This is a CONCAT_VECTORS.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 1868 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
2171 case ISD::CONCAT_VECTORS:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 8326 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops);
|
