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    Searched refs:CPLL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
xlnx-versal-clk.h 37 #define CPLL 26
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
exynos5422-odroid-core.dtsi 67 /* derived from 666MHz CPLL */
85 /* derived from 666MHz CPLL */
112 /* derived from 666MHz CPLL */
151 /* derived from 666MHz CPLL */
160 /* derived from 666MHz CPLL */
217 /* derived from 666MHz CPLL */
277 /* derived from 666MHz CPLL */
  /src/sys/arch/arm/samsung/
exynos_soc.c 434 DUMP_PLL(5, CPLL);
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/
rk3328.dtsi 771 * CPLL should run at 1200, but that is to high for
773 * We need set cpll child clk div first,
774 * and then set the cpll frequency.

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