| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| aarch64-sim.h | 36 uint32_t CPSR;
|
| cpustate.c | 261 /* Retrieve the CPSR register as an int. */
265 return AARCH64_SIM_CPU (cpu)->CPSR;
268 /* Set the CPSR register as an int. */
276 if (aarch64_cpu->CPSR != new_flags)
278 "CPSR changes from %s to %s",
279 decode_cpsr (aarch64_cpu->CPSR), decode_cpsr (new_flags));
282 "CPSR stays at %s", decode_cpsr (aarch64_cpu->CPSR));
285 aarch64_cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
288 /* Read a specific subset of the CPSR as a bit pattern. *
[all...] |
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| aarch64-sim.h | 36 uint32_t CPSR;
|
| cpustate.c | 261 /* Retrieve the CPSR register as an int. */
265 return AARCH64_SIM_CPU (cpu)->CPSR;
268 /* Set the CPSR register as an int. */
276 if (aarch64_cpu->CPSR != new_flags)
278 "CPSR changes from %s to %s",
279 decode_cpsr (aarch64_cpu->CPSR), decode_cpsr (new_flags));
282 "CPSR stays at %s", decode_cpsr (aarch64_cpu->CPSR));
285 aarch64_cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
288 /* Read a specific subset of the CPSR as a bit pattern. *
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MVETailPredUtils.h | 106 MIB.addReg(ARM::CPSR, RegState::Define);
114 MIB.addReg(ARM::CPSR);
142 MIB.addReg(ARM::CPSR);
170 MIB.addReg(ARM::CPSR);
|
| Thumb2SizeReduction.cpp | 74 // 2 - Always set CPSR.
217 // Last instruction to define CPSR in the current block.
219 // Was CPSR last defined by a high latency instruction?
220 // When CPSRDef is null, this refers to CPSR defs in predecessors.
256 if (*Regs == ARM::CPSR)
272 /// the 's' 16-bit instruction partially update CPSR. Abort the
273 /// transformation to avoid adding false dependency on last CPSR setting
277 /// last instruction that defines the CPSR and the current instruction. If there
279 /// before the CPSR setting instruction anyway.
304 if (Reg == 0 || Reg == ARM::CPSR)
[all...] |
| Thumb1InstrInfo.cpp | 60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
64 ->addRegisterDead(ARM::CPSR, RegInfo);
145 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
|
| Thumb2ITBlockPass.cpp | 155 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
|
| ARMBaseInstrInfo.cpp | 497 // For conditional branches, we use addOperand to preserve CPSR flags.
590 // Thumb 1 arithmetic instructions do not set CPSR when executed inside an
594 assert(MCID.OpInfo[1].isOptionalDef() && "CPSR def isn't expected operand");
596 MI.getOperand(1).getReg() != ARM::CPSR) &&
597 "if conversion tried to stop defining used CPSR");
638 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
639 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
642 // Filter out T1 instructions that have a dead CPSR,
659 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
738 if (MO.getReg() != ARM::CPSR)
[all...] |
| ARMFastISel.cpp | 234 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
245 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
246 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
250 // Look to see if our OptionalDef is defining CPSR or CCR.
253 if (MO.getReg() == ARM::CPSR)
254 *CPSR = true;
277 // CPSR defs that need to be added before the remaining operands. See s_cc_out
290 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
291 bool CPSR = false
[all...] |
| ARMInstructionSelector.cpp | 602 .add(predOps(Cond, ARM::CPSR));
796 .add(predOps(ARMCC::EQ, ARM::CPSR));
1154 .add(predOps(ARMCC::NE, ARM::CPSR));
|
| MVETPAndVPTOptimisationsPass.cpp | 195 MIB.addReg(ARM::CPSR, RegState::Define);
204 MIB.addReg(ARM::CPSR);
|
| ARMAsmPrinter.cpp | 1725 .addReg(ARM::CPSR)
1781 .addReg(ARM::CPSR)
1912 .addReg(ARM::CPSR)
1931 .addReg(ARM::CPSR)
1946 .addReg(ARM::CPSR)
|
| ARMExpandPseudoInsts.cpp | 1031 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1155 .addReg(ARM::CPSR, RegState::Kill);
1644 .addReg(ARM::CPSR, RegState::Kill);
1667 .addReg(ARM::CPSR, RegState::Kill);
1759 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1765 .addReg(ARM::CPSR, RegState::Kill);
1787 .addReg(ARM::CPSR, RegState::Kill);
2102 .addReg(ARM::CPSR, RegState::Define)
2304 .addReg(ARM::CPSR, RegState::Define);
2499 .addReg(ARM::CPSR, RegState::Undef)
[all...] |
| ARMLowOverheadLoops.cpp | 1316 // If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
1318 RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore);
1348 MIB.addReg(ARM::CPSR);
1359 MIB.addReg(ARM::CPSR);
|
| ARMISelLowering.cpp | 3110 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3357 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
4597 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4754 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4874 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5273 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5308 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5415 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5464 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5518 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32)
[all...] |
| Thumb1FrameLowering.cpp | 419 .addDef(ARM::CPSR)
425 .addDef(ARM::CPSR)
|
| ARMBaseInstrInfo.h | 183 // CPSR defined in instruction
553 /// This operand will always refer to CPSR and it will have the Define flag set.
556 return MachineOperand::CreateReg(ARM::CPSR,
773 /// CPSR def operand.
|
| /src/sys/arch/dreamcast/dev/microcode/ |
| aica_arm_locore.S | 45 mrs r0,CPSR /* disable interrupt */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 191 if (MO.isReg() && MO.getReg() == ARM::CPSR &&
239 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
|
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| armemu.h | 168 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
170 #define CPSR (ECC | EINT | EMODE)
|
| /src/external/gpl3/gdb/dist/gdb/stubs/ |
| sparc-stub.c | 119 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR };
230 ! CPSR and FPSR not impl
662 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
675 8 * 4, 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
| /src/external/gpl3/gdb.old/dist/gdb/stubs/ |
| sparc-stub.c | 119 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR };
230 ! CPSR and FPSR not impl
662 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
675 8 * 4, 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
| /src/sys/external/bsd/gnu-efi/dist/inc/ |
| efidebug.h | 505 UINT32 CPSR;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 1025 case Sparc::CPSR:
1168 RegNo = Sparc::CPSR;
|
