| /src/sys/arch/hpc/conf/ |
| platid.def | 37 * CPU definitions
39 CPU:
100 CPU=MIPS_VR_4102 11 -"11" 12 -"12" 13 -"13"
104 CPU=MIPS_VR_41XX
106 CPU=MIPS_VR_4111 300 -"300"
107 CPU=MIPS_VR_4121 320 -"320"
108 CPU=MIPS_VR_4111 forDoCoMo --" MobileGearII for DoCoMo"
109 CPU=MIPS_VR_4102 mpro700 --" MobilePro 700"
110 CPU=MIPS_VR_4121 330 -"330"
113 CPU=MIPS_VR_4111 500 -"500
[all...] |
| /src/sys/arch/epoc32/stand/e32boot/ldd/ |
| cpu.h | 1 /* $NetBSD: cpu.h,v 1.1 2013/04/28 12:11:27 kiyohara Exp $ */
28 class CPU {
34 class ARM7 : public CPU {
40 class ARM7TDMI : public CPU {
46 class SA1100 : public CPU {
|
| epoc32.h | 32 CPU *cpu; member in class:EPOC32
|
| /src/sys/arch/sh3/include/ |
| endian_machdep.h | 4 # error Define SH target CPU endian-ness in port-specific header file.
|
| /src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| xray_powerpc64.inc | 22 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT {
23 CPU = 0;
|
| xray_x86_64.inc | 22 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT {
26 CPU = LongCPU;
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| xray_tsc.h | 29 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT {
30 CPU = 0;
50 // or slower depending on CPU turbo or power saving mode. Furthermore,
68 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT {
76 CPU = 0;
88 #endif // CPU architecture
|
| xray_fdr_controller.h | 85 // buffer, associated with a particular thread, with a new CPU. For the
148 uint16_t CPU) XRAY_NEVER_INSTRUMENT {
149 if (UNLIKELY(LatestCPU != CPU || LatestTSC == 0)) {
150 // We update our internal tracking state for the Latest TSC and CPU we've
153 LatestCPU = CPU;
158 W.writeMetadata<MetadataRecord::RecordKinds::NewCPUId>(CPU, TSC);
162 DCHECK_EQ(LatestCPU, CPU);
183 uint16_t CPU) XRAY_NEVER_INSTRUMENT {
246 uint16_t CPU) XRAY_NEVER_INSTRUMENT {
251 auto PreambleStatus = recordPreamble(TSC, CPU);
[all...] |
| xray_fdr_logging.cc | 154 // Version 4 includes CPU data in the custom event records.
156 // and removes the CPU data in custom event records (similar to how
158 // metadata records for TSC wraparound and CPU migration).
162 // Test for required CPU features and cache the cycle frequency
414 unsigned char CPU = 0;
419 // we've seen this CPU before. We also do it before we load anything else,
423 // Test once for required CPU features
430 Result.TSC = __xray::readTSC(Result.CPU);
439 Result.CPU = 0;
500 auto &CPU = TC.CPU
[all...] |
| xray_basic_logging.cc | 51 uint8_t CPU;
173 uint8_t CPU = 0;
174 uint64_t TSC = ReadTSC(CPU);
183 // When we encounter an entry event, we keep track of the TSC and the CPU,
187 E.CPU = CPU;
207 // - The CPU is the same as the most recent entry in the stack.
217 if (StackTop.FuncId == FuncId && StackTop.CPU == CPU &&
238 R.CPU = CPU
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/lib/xray/tests/unit/ |
| fdr_controller_test.cc | 85 uint16_t CPU = 1;
86 ASSERT_TRUE(C->functionEnter(FId, TSC++, CPU));
87 ASSERT_TRUE(C->functionExit(FId, TSC++, CPU));
88 ASSERT_TRUE(C->functionEnterArg(FId, TSC++, CPU, 1));
89 ASSERT_TRUE(C->functionTailExit(FId, TSC++, CPU));
144 uint16_t CPU = 0;
145 ASSERT_TRUE(C->functionEnter(1, TSC++, CPU));
146 ASSERT_TRUE(C->functionEnter(2, TSC++, CPU));
147 ASSERT_TRUE(C->functionExit(2, TSC++, CPU));
148 ASSERT_TRUE(C->functionExit(1, TSC += 1000, CPU));
[all...] |
| test_helpers.cc | 46 *OS << "XRayRecord { CPU = " << R.CPU
|
| /src/sys/arch/hpc/hpc/ |
| platid.awk | 52 if (mode != MACH && mode != CPU) {
85 if (mode == CPU) {
101 if (mode == CPU) {
127 CPU = 1
137 mode_name[CPU] = "CPU"
140 shifts[CPU, 0] = "PLATID_CPU_ARCH_SHIFT"
141 shifts[CPU, 1] = "PLATID_CPU_SERIES_SHIFT"
142 shifts[CPU, 2] = "PLATID_CPU_MODEL_SHIFT"
143 shifts[CPU, 3] = "PLATID_CPU_SUBMODEL_SHIFT
[all...] |
| /src/sys/arch/mips/include/ |
| endian_machdep.h | 29 # error Define MIPS target CPU endian-ness in port-specific header file.
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/ |
| r8a779a0-falcon.dts | 3 * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
9 #include "r8a779a0-falcon-cpu.dtsi"
14 model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
15 compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
|
| r8a779a0-falcon-cpu.dtsi | 3 * Device Tree Source for the Falcon CPU board
14 model = "Renesas Falcon CPU board";
15 compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
105 label = "cpu-board";
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6q-skov-revc-lt2.dts | 7 #include "imx6qdl-skov-cpu.dtsi"
8 #include "imx6qdl-skov-cpu-revc.dtsi"
11 model = "SKOV IMX6 CPU QuadCore";
|
| sunxi-bananapi-m2-plus-v1.2.dtsi | 11 * resistance on the CPU regulator's feedback pin.
29 cpu-supply = <®_vdd_cpux>;
33 cpu-supply = <®_vdd_cpux>;
37 cpu-supply = <®_vdd_cpux>;
41 cpu-supply = <®_vdd_cpux>;
|
| armada-388-clearfog.dts | 19 /* CON2, nearest CPU, USB2 only. */
26 /* Port 2, Lane 0. CON2, nearest CPU. */
132 label = "cpu";
|
| kirkwood-blackarmor-nas220.dts | 97 * pin 1 - TX (CPU's TX)
98 * pin 4 - RX (CPU's RX)
|
| /src/sys/arch/arm/arm/ |
| cpufunc_asm_pj4b.S | 58 dsb @ Erratum#ARM-CPU-4742
66 bic r0, r0, #(1 << 12) @ Erratum#ARM-CPU-6136
73 bic r0, r0, #(1 << 2) @ Erratum#ARM-CPU-6409
|
| /src/sys/arch/hpcarm/hpcarm/ |
| kloader_machdep.c | 101 #error No support KLOADER with specific CPU type.
|
| /src/sys/external/bsd/compiler_rt/dist/include/xray/ |
| xray_records.h | 79 // The CPU where the thread is running. We assume number of CPUs <= 256.
80 uint8_t CPU = 0;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/hisilicon/ |
| hi6220-coresight.dtsi | 223 cpu = <&cpu0>;
242 cpu = <&cpu1>;
261 cpu = <&cpu2>;
280 cpu = <&cpu3>;
299 cpu = <&cpu4>;
318 cpu = <&cpu5>;
337 cpu = <&cpu6>;
356 cpu = <&cpu7>;
378 /* CTI - CPU-0 */
387 cpu = <&cpu0>
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/mti/ |
| sead3.dts | 26 cpu@0 {
37 compatible = "mti,cpu-interrupt-controller";
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
|
