HomeSort by: relevance | last modified time | path
    Searched refs:CP_HQD_PQ_CONTROL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 308 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
309 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
amdgpu_amdkfd_gfx_v9.c 298 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
299 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
amdgpu_gfx_v10_0.c 3290 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3292 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3295 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3297 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3298 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3299 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3300 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3301 mqd->cp_hqd_pq_control = tmp;
3415 mqd->cp_hqd_pq_control);
amdgpu_gfx_v8_0.c 4485 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4487 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4490 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4492 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4494 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4496 mqd->cp_hqd_pq_control = tmp;
amdgpu_gfx_v9_0.c 3398 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3400 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3403 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3405 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3406 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3407 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3408 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3409 mqd->cp_hqd_pq_control = tmp;
3522 mqd->cp_hqd_pq_control);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 1521 #define CP_HQD_PQ_CONTROL 0xC958
radeon_cik.c 4478 u32 cp_hqd_pq_control; member in struct:hqd_registers
4685 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4686 mqd->queue_state.cp_hqd_pq_control &=
4689 mqd->queue_state.cp_hqd_pq_control |=
4691 mqd->queue_state.cp_hqd_pq_control |=
4694 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4696 mqd->queue_state.cp_hqd_pq_control &=
4698 mqd->queue_state.cp_hqd_pq_control |=
4700 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control)
    [all...]

Completed in 69 milliseconds