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    Searched refs:CP_INT_CNTL_RING0 (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 1776 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1778 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1780 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1782 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4837 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4843 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4990 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5009 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
amdgpu_gfx_v9_0.c 2565 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2566 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2567 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2568 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
5385 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5455 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5474 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5499 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5508 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
amdgpu_gfx_v8_0.c 3884 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3885 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3886 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3887 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
6513 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6573 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6584 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6650 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
sid.h 1307 #define CP_INT_CNTL_RING0 0x306A
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si.c 5155 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5163 WREG32(CP_INT_CNTL_RING0, tmp);
5960 tmp = RREG32(CP_INT_CNTL_RING0) &
5962 WREG32(CP_INT_CNTL_RING0, tmp);
6078 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6110 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
radeon_cik.c 5788 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5794 WREG32(CP_INT_CNTL_RING0, tmp);
6887 tmp = RREG32(CP_INT_CNTL_RING0) &
6889 WREG32(CP_INT_CNTL_RING0, tmp);
7065 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
7245 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
cikd.h 1333 #define CP_INT_CNTL_RING0 0xC1A8
sid.h 1278 #define CP_INT_CNTL_RING0 0xC1A8

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