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Searched refs:CP_ME1_PIPE0_INT_CNTL (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h	`1360 #define CP_ME1_PIPE0_INT_CNTL 0xC214`
radeon_cik.c	`6896 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); 7079 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; 7250 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`4890 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4896 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,`
amdgpu_gfx_v9_0.c	`5432 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5438 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,`
amdgpu_gfx_v8_0.c	`6654 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,`

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