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    Searched refs:CP_ME1_PIPE3_INT_CNTL (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 1363 #define CP_ME1_PIPE3_INT_CNTL 0xC220
radeon_cik.c 6899 WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
7082 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7253 WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 6660 WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

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