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    Searched refs:CP_ME2_PIPE0_INT_CNTL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 1364 #define CP_ME2_PIPE0_INT_CNTL 0xC224
radeon_cik.c 6900 WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
7083 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7254 WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 5094 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5104 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
amdgpu_gfx_v8_0.c 6662 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

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