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Searched refs:CP_MEC_CNTL (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu8_smumgr.c	`200 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); 201 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);`
/src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h	`1096 #define CP_MEC_CNTL 0x8234 1100 #define CP_MEC_CNTL 0x8234`
radeon_cik.c	`4247 WREG32(CP_MEC_CNTL, 0); 4258 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT \| MEC_ME2_HALT)); 4977 WREG32(CP_MEC_CNTL, MEC_ME1_HALT \| MEC_ME2_HALT); 5181 WREG32(CP_MEC_CNTL, MEC_ME1_HALT \| MEC_ME2_HALT);`

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