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Searched refs:CP_MEC_CNTL__MEC_ME1_HALT_MASK (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v7_0.c	`2716 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK \| CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 4676 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK \| CP_MEC_CNTL__MEC_ME2_HALT_MASK);`
amdgpu_gfx_v10_0.c	`2885 (CP_MEC_CNTL__MEC_ME1_HALT_MASK \|`
amdgpu_gfx_v8_0.c	`4327 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK \| CP_MEC_CNTL__MEC_ME2_HALT_MASK));`
amdgpu_gfx_v9_0.c	`3254 (CP_MEC_CNTL__MEC_ME1_HALT_MASK \| CP_MEC_CNTL__MEC_ME2_HALT_MASK));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_2_sh_mask.h	`2227 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000`
gfx_8_0_sh_mask.h	`2773 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 [all...]`
gfx_8_1_sh_mask.h	`3295 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_sh_mask.h	`850 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L [all...]`
gc_9_1_sh_mask.h	`749 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L [all...]`
gc_9_2_1_sh_mask.h	`738 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L [all...]`
gc_10_1_0_sh_mask.h	`6325 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L [all...]`

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