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    Searched refs:CP_ME_CNTL (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ni.c 1471 WREG32(CP_ME_CNTL, 0);
1475 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1853 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
rv770d.h 337 #define CP_ME_CNTL 0x86D8
nid.h 320 #define CP_ME_CNTL 0x86D8
cikd.h 1110 #define CP_ME_CNTL 0x86D8
sid.h 1029 #define CP_ME_CNTL 0x86D8
radeon_si.c 3474 WREG32(CP_ME_CNTL, 0);
3478 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3887 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4056 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
radeon_evergreen.c 3023 WREG32(CP_ME_CNTL, cp_me);
3914 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
4024 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
evergreend.h 463 #define CP_ME_CNTL 0x86D8
radeon_cik.c 3893 WREG32(CP_ME_CNTL, 0);
3897 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
4974 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
5178 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
radeon_rv770.c 1092 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 4126 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4127 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4128 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4130 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
amdgpu_gfx_v10_0.c 2398 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2399 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2400 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
amdgpu_gfx_v9_0.c 3046 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
3047 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
3048 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
sid.h 1028 #define CP_ME_CNTL 0x21B6

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