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    Searched refs:CP_PQ_WPTR_POLL_CNTL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 1357 #define CP_PQ_WPTR_POLL_CNTL 0xC20C
radeon_cik.c 4218 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4220 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4637 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4639 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4702 /* only used if CP_PQ_WPTR_POLL_CNTL.WPTR_POLL_EN=1 */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 3417 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3471 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3530 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3852 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
amdgpu_gfx_v10_0.c 3309 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3363 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3423 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
amdgpu_gfx_v7_0.c 2996 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3067 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
amdgpu_gfx_v8_0.c 4504 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4588 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);

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