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    Searched refs:CP_RB0_CNTL (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
nid.h 486 #define CP_RB0_CNTL 0xC104
cikd.h 1304 #define CP_RB0_CNTL 0xC104
sid.h 1248 #define CP_RB0_CNTL 0xC104
radeon_si.c 3681 WREG32(CP_RB0_CNTL, tmp);
3684 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3700 WREG32(CP_RB0_CNTL, tmp);
radeon_ni.c 1639 CP_RB0_CNTL,
radeon_cik.c 4101 WREG32(CP_RB0_CNTL, tmp);
4104 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4119 WREG32(CP_RB0_CNTL, tmp);
4684 /* set up the HQD, this is similar to CP_RB0_CNTL */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 4282 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4283 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4284 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4285 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4287 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4483 /* set up the HQD, this is similar to CP_RB0_CNTL */
amdgpu_gfx_v10_0.c 2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2794 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3033 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3288 /* set up the HQD, this is similar to CP_RB0_CNTL */
3413 /* set up the HQD, this is similar to CP_RB0_CNTL */
amdgpu_gfx_v9_0.c 3192 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3193 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3195 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3396 /* set up the HQD, this is similar to CP_RB0_CNTL */
3520 /* set up the HQD, this is similar to CP_RB0_CNTL */
sid.h 1277 #define CP_RB0_CNTL 0x3041

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