| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_cursor.c | 36 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
38 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
39 crtcstate->CRTC[index]);
48 struct drm_crtc *crtc = &nv_crtc->base; local in function:nv04_cursor_set_offset
50 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
55 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
56 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
58 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24
[all...] |
| nouveau_dispnv04_crtc.c | 53 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
57 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
59 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
60 crtcstate->CRTC[index]);
63 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
66 struct drm_device *dev = crtc->dev;
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
70 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev))
1041 struct drm_crtc *crtc; member in struct:nv04_page_flip_state
[all...] |
| nouveau_dispnv04_tvnv04.c | 93 int head = nouveau_crtc(encoder->crtc)->index;
117 state->CRTC[NV_CIO_CRE_49] |= 0x10;
119 state->CRTC[NV_CIO_CRE_49] &= ~0x10;
122 state->CRTC[NV_CIO_CRE_LCD__INDEX]);
124 state->CRTC[NV_CIO_CRE_49]);
132 int head = nouveau_crtc(encoder->crtc)->index;
150 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
157 * they might be useful if we ever allow a CRTC to drive
174 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
179 NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n"
[all...] |
| disp.h | 23 uint8_t CRTC[0xa0];
170 struct dcb_output *outp, int crtc)
174 init.head = crtc;
|
| nouveau_dispnv04_dfp.c | 62 /* special case of nv_read_tmds to find crtc associated with an output.
104 /* digital remnants must be cleaned before new crtc
114 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
121 struct drm_crtc *crtc; local in function:nv04_dfp_update_fp_control
126 nv_crtc = nouveau_crtc(encoder->crtc);
140 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
141 nv_crtc = nouveau_crtc(crtc);
254 int head = nouveau_crtc(encoder->crtc)->index;
256 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
257 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]
520 struct drm_crtc *crtc = encoder->crtc; local in function:nv04_lvds_dpms
[all...] |
| nouveau_dispnv04_tvnv17.c | 407 int head = nouveau_crtc(encoder->crtc)->index;
408 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
428 !enc->crtc &&
468 int head = nouveau_crtc(encoder->crtc)->index;
474 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
475 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
581 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
606 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
694 struct drm_crtc *crtc = encoder->crtc; local in function:nv17_tv_set_property
[all...] |
| hw.h | 310 /* renders the extended crtc regs (cr19+) on all crtcs impervious:
347 * for changes to the CRTC CURCTL regs to take effect, whether changing
378 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
|
| nouveau_dispnv04_hw.c | 425 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
432 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
|
| /src/sys/arch/x68k/dev/ |
| ite_tv.c | 56 #define CRTC (IODEVbase->io_crtc)
108 uint16_t saved_r21 = CRTC.r21;
121 CRTC.r21 = (mode & 0x0f) | 0x0100;
128 CRTC.r22 = (src << 8) | dst; /* specify raster number */
130 CRTC.crtctrl = 0x0008;
141 CRTC.crtctrl = 0x0000;
143 CRTC.r21 = saved_r21;
274 CRTC.r21 = 0x0100 | ip->fgcolor << 4;
280 CRTC.r21 ^= 0x00f0;
289 /* crtc mode reset *
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_hwseq.h | 92 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
93 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
105 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
111 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
124 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
134 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
135 HWSEQ_PHYPLL_REG_LIST(CRTC), \
148 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
149 HWSEQ_PHYPLL_REG_LIST(CRTC), \
[all...] |
| dce_ipp.h | 60 SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
|
| dce_transform.h | 101 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
105 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
106 SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 152 IRQ_REG_ENTRY(CRTC, reg_num,\
160 IRQ_REG_ENTRY(CRTC, reg_num,\
|
