HomeSort by: relevance | last modified time | path
    Searched refs:CR_RST (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/arch/sandpoint/stand/altboot/
sip.c 64 #define CR_RST (1U << 8) /* software reset */
152 CSR_WRITE(l, SIP_CR, CR_RST);
155 } while (val & CR_RST); /* S1C */
  /src/sys/arch/mac68k/obio/
if_sn_obio.c 204 CSR_WRITE(sc, SONIC_CR, CR_RST);
  /src/sys/dev/ic/
dp83932reg.h 171 #define CR_RST (1U << 7) /* Software Reset */
dp83932.c 878 CSR_WRITE(sc, SONIC_CR, CR_RST);
921 CSR_WRITE(sc, SONIC_CR, CR_RST);
  /src/sys/arch/newsmips/apbus/
if_snreg.h 89 * With the exception of CR_RST, the bit is reset when the operation
94 #define CR_RST 0x0080 /* software reset */
105 * reset mode (s_cr.CR_RST is set.)
if_sn.c 122 NIC_PUT(sc, SNR_CR, CR_RST);
376 NIC_PUT(sc, SNR_CR, CR_RST); /* DCR only accessible in reset mode! */
448 NIC_PUT(sc, SNR_CR, CR_RST);
699 NIC_PUT(sc, SNR_CR, CR_RST);
  /src/sys/dev/pci/
if_sipreg.h 210 #define CR_RST 0x00000100 /* software reset */
if_sip.c 2526 bus_space_write_4(st, sh, SIP_CR, CR_RST);
2529 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0)

Completed in 35 milliseconds