| /src/sys/arch/cobalt/stand/boot/ |
| ns16550.c | 39 #define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg)))
71 while ((CSR_READ(com_port, com_lsr) & LSR_TXRDY) == 0)
82 while ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0)
85 return CSR_READ(com_port, com_data);
93 if ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0)
96 return CSR_READ(com_port, com_data);
|
| lcd.c | 40 #define CSR_READ(base, reg) \
|
| tlp.c | 56 #define CSR_READ(l, r) (*(volatile uint32_t *)((l)->csr + (r)))
197 val = CSR_READ(l, TLP_BMR);
202 (void)CSR_READ(l, TLP_BMR);
423 ret = (ret << 1) | !!(CSR_READ(l, TLP_APROM) & VV);
|
| /src/sys/dev/ic/ |
| pca9564.c | 59 #define CSR_READ(sc, r) (*sc->sc_ios.read_byte)(sc->sc_dev, r)
123 control = CSR_READ(sc, PCA9564_I2CCON);
141 control = CSR_READ(sc, PCA9564_I2CCON);
153 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA)));
155 if (CSR_READ(sc, PCA9564_I2CCON) & I2CCON_SI)
159 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA)));
173 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA)));
174 control = CSR_READ(sc, PCA9564_I2CCON);
178 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA)));
189 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA)))
[all...] |
| dp83932.c | 582 isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr;
1080 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP | CR_RXEN | CR_ST)) == 0)
1084 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP | CR_RXEN | CR_ST)) != 0)
1265 if ((CSR_READ(sc, SONIC_CR) & CR_LCAM) == 0)
1269 if (CSR_READ(sc, SONIC_CR) & CR_LCAM)
|
| dp83932var.h | 207 #define CSR_READ(sc, reg) \
|
| /src/sys/arch/mmeye/stand/boot/ |
| com.c | 102 #define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg)))
162 while ((CSR_READ(com_port, com_lsr) & LSR_TXRDY) == 0)
173 while ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0)
176 return CSR_READ(com_port, com_data);
184 if ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0)
187 return CSR_READ(com_port, com_data);
|
| /src/sys/dev/pci/ |
| if_wm.c | 791 #define CSR_READ(sc, reg) \
796 (void)CSR_READ((sc), WMREG_STATUS)
1874 if (CSR_READ(sc, reg) & SCTL_CTL_READY)
2303 sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
2349 reg = CSR_READ(sc, WMREG_STATUS);
2423 CSR_READ(sc, WMREG_COLC);
2424 CSR_READ(sc, WMREG_RXERRC);
2450 reg = CSR_READ(sc, WMREG_EECD);
2466 reg = CSR_READ(sc, WMREG_EECD);
2592 (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1
[all...] |
| if_dge.c | 365 #define CSR_READ(sc, reg) \
756 reg = CSR_READ(sc, DGE_STATUS);
1525 icr = CSR_READ(sc, DGE_ICR);
1822 status = CSR_READ(sc, DGE_STATUS);
1856 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0)
1861 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST)
1990 reg = CSR_READ(sc, DGE_RXCSUM);
2278 hash = CSR_READ(sc, DGE_MTA + (reg << 2));
2326 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK | EECD_DI | EECD_CS);
2362 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_SK)
[all...] |
| /src/sys/arch/sandpoint/stand/altboot/ |
| sme.c | 47 #define CSR_READ(l, r) in32rb((l)->csr+(r))
132 mac32 = CSR_READ(l, ADDRL);
133 mac16 = CSR_READ(l, ADDRH);
281 ctl = CSR_READ(l, MIIADDR);
286 ctl = CSR_READ(l, MIIADDR);
288 return CSR_READ(l, MIIDATA);
297 ctl = CSR_READ(l, MIIADDR);
|
| tlp.c | 47 #define CSR_READ(l, r) in32rb((l)->csr+(r))
144 } while (i-- > 0 && (CSR_READ(l, PAR_CSR0) & PAR_SWR) != 0);
153 val = CSR_READ(l, PAR0_CSR25);
158 val = CSR_READ(l, PAR1_CSR26);
169 val = CSR_READ(l, AN_OMODE);
315 rv = (rv << 1) | !!(CSR_READ(l, SPR_CSR9) & MII_MDI);
|
| wm.c | 49 #define CSR_READ(l, r) in32rb((l)->csr+(r))
312 v = CSR_READ(l, WMREG_EECD) & ~(EECD_SK | EECD_DI);
338 data = (data << 1) | !!(CSR_READ(l, WMREG_EECD) & EECD_DO);
343 v = CSR_READ(l, WMREG_EECD) & ~EECD_CS;
361 data = CSR_READ(l, WMREG_MDIC);
374 data = CSR_READ(l, WMREG_MDIC);
|
| sip.c | 47 #define CSR_READ(l, r) in32rb((l)->csr+(r))
154 val = CSR_READ(l, SIP_CR);
187 val = CSR_READ(l, SIP_CFG);
328 data = (data << 1) | !!(CSR_READ(l, SIP_MEAR) & MEAR_EEDO);
361 val = CSR_READ(l, SIP_BMCR + (reg << 2));
|
| /src/sys/arch/mac68k/obio/ |
| if_sn_obio.c | 209 i = CSR_READ(sc, SONIC_CAP2);
215 i = CSR_READ(sc, SONIC_CAP1);
221 i = CSR_READ(sc, SONIC_CAP0);
|
| /src/sys/arch/sandpoint/sandpoint/ |
| satmgr.c | 188 #define CSR_READ(t,r) bus_space_read_1((t)->sc_iot, (t)->sc_ioh, (r))
458 lsr = CSR_READ(sc, LSR);
646 iir = CSR_READ(sc, IIR) & IIR_IMASK;
664 iir = CSR_READ(sc, IIR) & IIR_IMASK;
675 lsr = CSR_READ(sc, LSR);
681 (void) CSR_READ(sc, RBR);
683 lsr = CSR_READ(sc, LSR);
686 ch = CSR_READ(sc, RBR);
693 lsr = CSR_READ(sc, LSR);
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| main.c | 44 #define CSR_READ(reg) \
123 socmodel = CSR_READ(S3C2440_GPIO_BASE + GPIO_GSTATUS1);
472 stat = CSR_READ(S3C2440_UART_BASE(0) + SSCOM_UTRSTAT);
|
| /src/sys/arch/arm/sociox/ |
| if_scx.c | 544 #define CSR_READ(sc,off) \
605 val = CSR_READ(sc, reg);
622 return CSR_READ(sc, MACDATA);
882 which = CSR_READ(sc, HWVER); /* Socionext version 5.xx */
1533 status = CSR_READ(sc, xINTSR); /* not W1C */
1534 enable = CSR_READ(sc, xINTAEN);
1540 status = CSR_READ(sc, RXISR);
1546 (void)CSR_READ(sc, RXAVAILCNT); /* clear IRQ_RX ? */
1549 status = CSR_READ(sc, TXISR);
1555 (void)CSR_READ(sc, TXDONECNT); /* clear IRQ_TX ? *
[all...] |
| sni_i2c.c | 137 #define CSR_READ(sc, reg) \
|
