| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 2365 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
2398 { ISD::CTTZ, MVT::v8i64, 10 },
2399 { ISD::CTTZ, MVT::v16i32, 14 },
2400 { ISD::CTTZ, MVT::v32i16, 12 },
2401 { ISD::CTTZ, MVT::v64i8, 9 },
2438 { ISD::CTTZ, MVT::v8i64, 20 },
2439 { ISD::CTTZ, MVT::v16i32, 28 },
2440 { ISD::CTTZ, MVT::v32i16, 24 },
2441 { ISD::CTTZ, MVT::v64i8, 18 },
2525 { ISD::CTTZ, MVT::v4i64, 10 }
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 657 CTTZ,
|
| BasicTTIImpl.h | 1309 case Intrinsic::cttz:
1835 case Intrinsic::cttz:
1836 ISDs.push_back(ISD::CTTZ);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 393 case ISD::CTTZ:
797 case ISD::CTTZ:
|
| SelectionDAGDumper.cpp | 425 case ISD::CTTZ: return "cttz";
|
| LegalizeDAG.cpp | 2686 case ISD::CTTZ:
4394 case ISD::CTTZ:
4399 // Zero extend the argument unless its cttz, then use any_extend.
4400 if (Node->getOpcode() == ISD::CTTZ ||
4406 if (Node->getOpcode() == ISD::CTTZ) {
|
| LegalizeIntegerTypes.cpp | 68 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
549 if (N->getOpcode() == ISD::CTTZ) {
2082 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
3003 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
|
| LegalizeVectorTypes.cpp | 79 case ISD::CTTZ:
970 case ISD::CTTZ:
3145 case ISD::CTTZ:
|
| SelectionDAG.cpp | 3163 case ISD::CTTZ:
4653 case ISD::CTTZ:
4771 case ISD::CTTZ:
5007 case ISD::CTTZ:
|
| TargetLowering.cpp | 7066 isOperationLegalOrCustom(ISD::CTTZ, VT)) {
7067 Result = DAG.getNode(ISD::CTTZ, dl, VT, Op);
7075 SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op);
7079 DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 129 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 112 setOperationAction(ISD::CTTZ, T, Custom);
172 setOperationAction(ISD::CTTZ, T, Custom);
1447 // Lower vector CTTZ into a computation using CTLZ (Hacker's Delight):
1448 // cttz(x) = bitwidth(x) - ctlz(~x & (x-1))
2073 case ISD::CTTZ:
2110 case ISD::CTTZ: return LowerHvxCttz(Op, DAG);
|
| HexagonISelLowering.cpp | 1564 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1565 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1635 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 104 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
105 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 374 setOperationAction(ISD::CTTZ, VT, Expand);
409 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
450 setOperationAction(ISD::CTTZ, VT, Expand);
780 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
1263 case ISD::CTTZ:
2322 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2370 // cttz(x) = lo_32(x) == 0 ? cttz(hi_32(x)) + 32 : cttz(lo_32(x))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 490 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
491 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
492 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 128 setOperationAction(ISD::CTTZ, MVT::i32, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 185 setOperationAction(ISD::CTTZ, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 277 setOperationAction(ISD::CTTZ, VT, Custom);
932 // NEON does not have single instruction CTTZ for vectors.
933 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
934 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
935 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
936 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
938 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
939 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
940 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
941 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1576 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1640 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 421 // CTPOP or CTTZ were introduced in P8/P9 respectively
428 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
429 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
431 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
432 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
760 setOperationAction(ISD::CTTZ, VT, Legal);
762 setOperationAction(ISD::CTTZ, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 420 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
421 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 133 setOperationAction(ISD::CTTZ, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 274 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
280 setOperationAction(ISD::CTTZ, XLenVT, Expand);
4733 case ISD::CTTZ:
4743 N->getOpcode() == ISD::CTTZ || N->getOpcode() == ISD::CTTZ_ZERO_UNDEF;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 177 // VE has no CTTZ, ROTL, ROTR operations.
178 setOperationAction(ISD::CTTZ, IntVT, Expand);
|
