| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| dmub_reg.h | 53 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
56 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
61 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
88 dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
115 dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
|
| amdgpu_dmub_dcn21.c | 40 #define CTX dmub
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_bios_parser_helper.c | 53 #define CTX \
54 bios->ctx
|
| /src/sys/external/bsd/compiler_rt/dist/lib/asan/scripts/ |
| asan_device_setup | 412 CTX=u:object_r:system_file:s0
414 CTX=u:object_r:zygote_exec:s0
422 install "$TMPDIR/app_process32" /system/bin 755 $CTX
423 install "$TMPDIR/app_process32.real" /system/bin 755 $CTX
424 install "$TMPDIR/app_process64" /system/bin 755 $CTX
425 install "$TMPDIR/app_process64.real" /system/bin 755 $CTX
435 install "$TMPDIR/app_process32" /system/bin 755 $CTX
436 install "$TMPDIR/app_process.wrap" /system/bin 755 $CTX
437 install "$TMPDIR/asanwrapper" /system/bin 755 $CTX
447 adb_shell chcon $CTX /system/bin/sh-from-zygot
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 35 * CTX ==> macro to ptr to dc_context
36 * eg. aud110->base.ctx
42 dm_read_reg(CTX, REG(reg_name))
45 dm_write_reg(CTX, REG(reg_name), value)
57 generic_reg_set_ex(CTX, \
159 generic_reg_get(CTX, REG(reg_name), \
163 generic_reg_get2(CTX, REG(reg_name), \
168 generic_reg_get3(CTX, REG(reg_name), \
174 generic_reg_get4(CTX, REG(reg_name), \
181 generic_reg_get5(CTX, REG(reg_name),
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_ipp.c | 44 #define CTX \
45 ippn10->base.ctx
67 struct dc_context *ctx,
73 ippn10->base.ctx = ctx;
84 struct dc_context *ctx,
90 ippn10->base.ctx = ctx;
|
| dcn10_dwb.c | 42 #define CTX \
43 dwbc10->base.ctx
122 struct dc_context *ctx,
128 dwbc10->base.ctx = ctx;
|
| amdgpu_dcn10_link_encoder.c | 45 #define CTX \
46 enc10->base.ctx
48 enc10->base.ctx->logger
106 struct dc_bios *bp = enc10->base.ctx->dc_bios;
651 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
680 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
684 enc10->base.ctx = init_data->ctx;
761 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
778 if (enc10->base.ctx->dc->debug.hdmi20_disable)
[all...] |
| amdgpu_dcn10_opp.c | 44 #define CTX \
45 oppn10->base.ctx
416 struct dc_context *ctx,
423 oppn10->base.ctx = ctx;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_vmid.c | 39 #define CTX \
40 vmid->ctx
|
| amdgpu_dcn20_dccg.c | 47 #define CTX \
48 dccg_dcn->base.ctx
50 dccg->ctx->logger
113 struct dc_context *ctx,
127 base->ctx = ctx;
|
| amdgpu_dcn20_link_encoder.c | 42 #define CTX \
43 enc10->base.ctx
45 enc10->base.ctx->logger
254 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
272 dm_read_reg(CTX, AUX_REG(reg_name))
275 dm_write_reg(CTX, AUX_REG(reg_name), val)
359 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
364 enc10->base.ctx = init_data->ctx;
441 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios
[all...] |
| amdgpu_dcn20_hubbub.c | 39 #define CTX \
40 hubbub1->base.ctx
49 #define CTX \
50 hubbub1->base.ctx
223 struct dc *dc = hubbub->ctx->dc;
589 if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
590 hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
599 hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
617 struct dc_context *ctx,
622 hubbub->base.ctx = ctx
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services.h | 49 struct dc_context *ctx,
61 const struct dc_context *ctx,
67 #define dm_read_reg(ctx, address) \
68 dm_read_reg_func(ctx, address, __func__)
72 #define dm_write_reg(ctx, address, value) \
73 dm_write_reg_func(ctx, address, value, __func__)
76 const struct dc_context *ctx,
87 cgs_write_register(ctx->cgs_device, address, value);
88 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
92 const struct dc_context *ctx,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hwseq.c | 44 #define CTX \
45 hws->ctx
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_generic.c | 47 #define CTX \
48 generic->base.base.ctx
102 struct dc_context *ctx)
104 dal_hw_gpio_construct(&pin->base, id, en, ctx);
110 struct dc_context *ctx,
125 dal_hw_generic_construct(*hw_generic, id, en, ctx);
|
| amdgpu_hw_hpd.c | 47 #define CTX \
48 hpd->base.base.ctx
126 struct dc_context *ctx)
128 dal_hw_gpio_construct(&pin->base, id, en, ctx);
134 struct dc_context *ctx,
149 dal_hw_hpd_construct(*hw_hpd, id, en, ctx);
|
| amdgpu_hw_ddc.c | 49 #define CTX \
50 ddc->base.base.ctx
228 struct dc_context *ctx)
230 dal_hw_gpio_construct(&ddc->base, id, en, ctx);
236 struct dc_context *ctx,
251 dal_hw_ddc_construct(*hw_ddc, id, en, ctx);
|
| amdgpu_hw_gpio.c | 42 #define CTX \
43 gpio->base.ctx
188 struct dc_context *ctx)
190 pin->base.ctx = ctx;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
| amdgpu_irq_service.c | 55 #define CTX \
56 irq_service->ctx
58 irq_service->ctx->logger
64 if (!init_data || !init_data->ctx) {
69 irq_service->ctx = init_data->ctx;
100 uint32_t value = dm_read_reg(irq_service->ctx, addr);
104 dm_write_reg(irq_service->ctx, addr, value);
137 uint32_t value = dm_read_reg(irq_service->ctx, addr);
141 dm_write_reg(irq_service->ctx, addr, value)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_hwseq.c | 36 #define CTX \
37 hws->ctx
|
| amdgpu_dce_ipp.c | 44 #define CTX \
45 ipp_dce->base.ctx
253 struct dc_context *ctx,
259 ipp_dce->base.ctx = ctx;
|
| amdgpu_dce_opp.c | 47 #define CTX \
48 opp110->base.ctx
550 struct dc_context *ctx,
558 opp110->base.ctx = ctx;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 45 #define CTX \
46 hws->ctx
88 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
98 value = dm_read_reg(ctx, addr);
115 dm_write_reg(ctx, addr, value);*/
118 value = dm_read_reg(ctx, addr);
150 dm_write_reg(ctx, addr, value);
165 struct dc_context *ctx = dc->ctx;
167 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr_internal.h | 74 #define CTX \
75 clk_mgr->base.ctx
77 clk_mgr->ctx->logger
|
