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    Searched refs:CURSOR0_CONTROL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_ipp.h 39 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
167 uint32_t CURSOR0_CONTROL;
amdgpu_dcn10_dpp.c 423 REG_UPDATE(CURSOR0_CONTROL,
435 REG_UPDATE_2(CURSOR0_CONTROL,
486 REG_UPDATE(CURSOR0_CONTROL,
dcn10_dpp.h 121 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
1335 uint32_t CURSOR0_CONTROL; \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dpp.c 246 REG_UPDATE(CURSOR0_CONTROL,
363 REG_UPDATE_3(CURSOR0_CONTROL,

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