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    Searched refs:CWL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
nouveau_nvkm_subdev_fb_sddr3.c 78 int CWL, CL, WR, DLL = 0, ODT = 0;
85 /* XXX: NV50: Get CWL from the timing register */
88 CWL = ram->next->bios.timing_10_CWL;
94 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
106 CWL = ramxlat(ramddr3_cwl, CWL);
109 if (CL < 0 || CWL < 0 || WR < 0)
124 ram->mr[2] |= (CWL & 0x07) << 3;
nouveau_nvkm_subdev_fb_gddr3.c 78 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi;
82 CWL = ram->next->bios.timing_10_CWL;
90 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
109 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
113 ram->mr[0] |= (CWL & 0x07) << 9;
nouveau_nvkm_subdev_fb_ramnv50.c 91 switch ((!T(CWL)) * ram->base.type) {
93 T(CWL) = T(CL) - 1;
96 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
103 timing[6] = (0x2d + T(CL) - T(CWL) +
105 T(CWL) << 8 |
106 (0x2f + T(CL) - T(CWL));
109 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 |
110 max_t(s8, T(CWL) - 2, 1) << 8 |
111 (0x2e + T(CL) - T(CWL));
115 timing[1] = (T(WR) + 1 + T(CWL)) << 24
    [all...]
nouveau_nvkm_subdev_fb_ramgt215.c 367 switch ((!T(CWL)) * ram->base.type) {
369 T(CWL) = T(CL) - 1;
372 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
380 timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
382 (T(WTR) + 1 + T(CWL)) << 8 |
383 (5 + T(CL) - T(CWL));
384 timing[2] = (T(CWL) - 1) << 24 |
398 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
401 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
402 (0x50 + T(CL) - T(CWL));
    [all...]

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