| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| cycles.s | 1 # Blackfin testcase for playing with CYCLES
10 CYCLES = R0;
13 /* CYCLES should be "small" while CYCLES2 should be R1 still */
14 R2 = CYCLES;
27 /* Test the "shadowed" CYCLES2 -- only a read of CYCLES reloads it */
34 R2 = CYCLES;
|
| push-pop.s | 81 # CYCLES can be user mode, but screws kernel
82 dmm_check CYCLES
|
| se_regmv_usp_sysreg.S | 22 // KLUDGE: from perl script must place cycles 2 write before cycles
23 // write, and cycles 2 read AFTER cycles read
91 // KLUDGE - moved read after that for cycles
96 CYCLES = USP;
97 R1 = CYCLES;
99 R1 = CYCLES2; // KLUDGE moved read after that for cycles
|
| se_popkill.S | 397 CYCLES = R7;
460 CYCLES = [ SP ++ ];
|
| run-tests.sh | 154 tmp=`grep -e CYCLES -e TESTSET -e CLI -e STI -e RTX -e RTI -e SEQSTAT $files -l`
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| cycles.s | 1 # Blackfin testcase for playing with CYCLES
10 CYCLES = R0;
13 /* CYCLES should be "small" while CYCLES2 should be R1 still */
14 R2 = CYCLES;
27 /* Test the "shadowed" CYCLES2 -- only a read of CYCLES reloads it */
34 R2 = CYCLES;
|
| push-pop.s | 81 # CYCLES can be user mode, but screws kernel
82 dmm_check CYCLES
|
| se_regmv_usp_sysreg.S | 22 // KLUDGE: from perl script must place cycles 2 write before cycles
23 // write, and cycles 2 read AFTER cycles read
91 // KLUDGE - moved read after that for cycles
96 CYCLES = USP;
97 R1 = CYCLES;
99 R1 = CYCLES2; // KLUDGE moved read after that for cycles
|
| se_popkill.S | 397 CYCLES = R7;
460 CYCLES = [ SP ++ ];
|
| run-tests.sh | 154 tmp=`grep -e CYCLES -e TESTSET -e CLI -e STI -e RTX -e RTI -e SEQSTAT $files -l`
|
| /src/external/gpl3/gdb/dist/gdb/stubs/ |
| sh-stub.c | 266 TICKS, STALLS, CYCLES, INSTS, PLR
|
| /src/external/gpl3/gdb/dist/sim/bfin/ |
| bfin-sim.h | 63 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4], cycles[3]; member in struct:bfin_cpu_state
84 /* How many cycles did this insn take to complete ? */
126 #define CYCLESREG (BFIN_CPU_STATE.cycles[0])
127 #define CYCLES2REG (BFIN_CPU_STATE.cycles[1])
128 #define CYCLES2SHDREG (BFIN_CPU_STATE.cycles[2])
202 #define SET_CYCLESREG(val) _SET_CORE32REG (CYCLES, val)
|
| /src/external/gpl3/gdb.old/dist/gdb/stubs/ |
| sh-stub.c | 266 TICKS, STALLS, CYCLES, INSTS, PLR
|
| /src/external/gpl3/gdb.old/dist/sim/bfin/ |
| bfin-sim.h | 63 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4], cycles[3]; member in struct:bfin_cpu_state
84 /* How many cycles did this insn take to complete ? */
126 #define CYCLESREG (BFIN_CPU_STATE.cycles[0])
127 #define CYCLES2REG (BFIN_CPU_STATE.cycles[1])
128 #define CYCLES2SHDREG (BFIN_CPU_STATE.cycles[2])
202 #define SET_CYCLESREG(val) _SET_CORE32REG (CYCLES, val)
|
