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    Searched refs:Cmov (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 2195 // M68k doesn't have an i8 cmov. If both operands are the result of a
2196 // truncate widen the cmov and push the truncate through. This avoids
2206 SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2207 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
2211 // M68kISD::CMOV means set the result (which is operand 1) to the RHS if
2215 return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2886 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
2887 // together with other CMOV pseudo-opcodes into a single basic-block with
2954 // This code lowers all pseudo-CMOV instructions. Generally it lowers thes
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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 448 // X86 wants to expand cmov itself.
5106 /// Is there a floating point cmov for the specific X86 condition code?
5107 /// Current x86 isa includes the following FP cmov instructions:
9210 // Perform the select in the scalar domain so we can use cmov.
22565 // Only perform this transform if CMOV is supported otherwise the select
22592 SDValue CMov = DAG.getNode(ISD::SELECT, DL, VT, Cmp, Add, N0);
22596 Created.push_back(CMov.getNode());
22600 DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i8));
23870 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
23871 // widen the cmov and push the truncate through. This avoids introducing a ne
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