HomeSort by: relevance | last modified time | path
    Searched refs:CmpMI (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ConditionOptimizer.cpp 112 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
113 void modifyCmp(MachineInstr *CmpMI, const CmpInfo &Info);
114 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
244 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {
245 unsigned Opc = CmpMI->getOpcode();
257 const int OldImm = (int)CmpMI->getOperand(2).getImm();
271 void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,
278 MachineBasicBlock *const MBB = CmpMI->getParent();
281 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc)
    [all...]
AArch64ConditionalCompares.cpp 157 MachineInstr *CmpMI;
187 bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
380 /// Only CmpMI is allowed to clobber the flags.
383 const MachineInstr *CmpMI) {
426 // Only CmpMI is allowed to clobber the flags.
427 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
558 CmpMI = findConvertibleCompare(CmpBB);
559 if (!CmpMI)
562 if (!canSpeculateInstrs(CmpBB, CmpMI)) {
649 // Now replace CmpMI with a ccmp instruction that also considers the incomin
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVEVPTBlockPass.cpp 72 MachineBasicBlock::iterator CmpMI = MI;
73 while (CmpMI != MI->getParent()->begin()) {
74 --CmpMI;
75 if (CmpMI->modifiesRegister(ARM::VPR, TRI))
77 if (CmpMI->readsRegister(ARM::VPR, TRI))
81 if (CmpMI == MI)
83 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode());
87 // Search forward from CmpMI to MI, checking if either register was def'd
88 if (registerDefinedBetween(CmpMI->getOperand(1).getReg(), std::next(CmpMI),
    [all...]
ARMBaseInstrInfo.cpp 2098 MachineInstr *CmpMI = findCMPToFoldIntoCBZ(LastMI, TRI);
2099 if (CmpMI)
5485 MachineBasicBlock::iterator CmpMI = Br;
5486 while (CmpMI != Br->getParent()->begin()) {
5487 --CmpMI;
5488 if (CmpMI->modifiesRegister(ARM::CPSR, TRI))
5490 if (CmpMI->readsRegister(ARM::CPSR, TRI))
5496 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri)
5498 Register Reg = CmpMI->getOperand(0).getReg()
    [all...]
ARMConstantIslandPass.cpp 1905 MachineInstr *CmpMI = findCMPToFoldIntoCBZ(Br.MI, TRI);
1906 if (!CmpMI || CmpMI->getOpcode() != ARM::tCMPi8)
1909 ImmCmp.MI = CmpMI;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILowerControlFlow.cpp 690 auto CmpMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_CMP_EQ_U32))
709 LIS->InsertMachineInstrInMaps(*CmpMI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 4311 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addUse(LHS);
4313 CmpMI.addUse(RHS);
4314 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
4315 return &*CmpMI;

Completed in 127 milliseconds