| /src/external/gpl3/binutils/dist/gas/config/ |
| xtensa-relax.h | 113 } CmpOp;
117 CmpOp cmp;
|
| xtensa-relax.c | 44 PRECOND ::= OPERAND CMPOP OPERAND
45 CMPOP ::= '==' | '!='
151 CmpOp cmpop; member in struct:precond_e_struct
611 CmpOp cmp,
627 CmpOp cmp,
1266 precond->cmpop = OP_EQUAL;
1284 precond->cmpop = OP_EQUAL;
1286 precond->cmpop = OP_NOTEQUAL;
1727 append_value_condition (tr, precond->cmpop,
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| xtensa-relax.h | 113 } CmpOp;
117 CmpOp cmp;
|
| xtensa-relax.c | 44 PRECOND ::= OPERAND CMPOP OPERAND
45 CMPOP ::= '==' | '!='
151 CmpOp cmpop; member in struct:precond_e_struct
611 CmpOp cmp,
627 CmpOp cmp,
1266 precond->cmpop = OP_EQUAL;
1284 precond->cmpop = OP_EQUAL;
1286 precond->cmpop = OP_NOTEQUAL;
1727 append_value_condition (tr, precond->cmpop,
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/FuzzMutate/ |
| Operations.h | 38 OpDescriptor cmpOpDescriptor(unsigned Weight, Instruction::OtherOps CmpOp,
|
| /src/external/apache2/llvm/dist/llvm/lib/FuzzMutate/ |
| Operations.cpp | 124 Instruction::OtherOps CmpOp,
126 auto buildOp = [CmpOp, Pred](ArrayRef<Value *> Srcs, Instruction *Inst) {
127 return CmpInst::Create(CmpOp, Pred, Srcs[0], Srcs[1], "C", Inst);
130 switch (CmpOp) {
136 llvm_unreachable("CmpOp must be ICmp or FCmp");
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostLegalizerLowering.cpp | 746 static unsigned getCmpOperandFoldingProfit(Register CmpOp,
749 if (!MRI.hasOneNonDBGUse(CmpOp))
766 MachineInstr *Def = getDefIgnoringCopies(CmpOp, MRI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 75 unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
186 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
219 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonBitSimplify.cpp | 2591 MachineOperand &CmpOp = MI->getOperand(2);
2592 if (!CmpOp.isImm() || CmpOp.getImm() != 0)
|
| HexagonInstrInfo.cpp | 3427 const MachineOperand &CmpOp = GA.getOperand(2);
3428 if (!CmpOp.isImm())
3430 int V = CmpOp.getImm();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPURegisterBankInfo.cpp | 897 unsigned CmpOp = OpSize % 64 == 0 ? AMDGPU::V_CMP_EQ_U64_e64
965 B.buildInstr(CmpOp)
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 2484 SDValue CmpOp = getValue(CB.CmpMHS);
2485 EVT VT = CmpOp.getValueType();
2488 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2492 VT, CmpOp, DAG.getConstant(Low, dl, VT));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 2968 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2969 // allowing Pos and Neg to be wider than CmpOp.
2970 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2975 (Pos == CmpOp ||
2977 Pos.getOperand(0) == CmpOp)));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 10445 SDValue CmpOp = Op.getOperand(2);
10448 if (DAG.MaskedValueIsZero(CmpOp, HighBits))
10454 DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
