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    Searched refs:CmpVT (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 4382 MVT CmpVT = N0.getSimpleValueType();
4383 MVT CmpSVT = CmpVT.getVectorElementType();
4403 bool Widen = !Subtarget->hasVLX() && !CmpVT.is512BitVector();
4461 unsigned Scale = CmpVT.is128BitVector() ? 4 : 2;
4462 unsigned SubReg = CmpVT.is128BitVector() ? X86::sub_xmm : X86::sub_ymm;
4463 unsigned NumElts = CmpVT.getVectorNumElements() * Scale;
4464 CmpVT = MVT::getVectorVT(CmpSVT, NumElts);
4467 CmpVT), 0);
4468 Src0 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src0);
4471 Src1 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src1)
    [all...]
X86ISelLowering.cpp 22389 EVT CmpVT = Op0.getValueType();
22391 assert((CmpVT == MVT::i8 || CmpVT == MVT::i16 ||
22392 CmpVT == MVT::i32 || CmpVT == MVT::i64) && "Unexpected VT!");
22396 if (CmpVT == MVT::i16 && !Subtarget.isAtom() &&
22423 CmpVT = MVT::i32;
22424 Op0 = DAG.getNode(ExtendOp, dl, CmpVT, Op0);
22425 Op1 = DAG.getNode(ExtendOp, dl, CmpVT, Op1);
22431 if (CmpVT == MVT::i64 && isa<ConstantSDNode>(Op1) && !isX86CCSigned(X86CC) &
    [all...]
X86FastISel.cpp 2081 EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType());
2083 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc()))
2314 EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType());
2315 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc()))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 10519 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
10526 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
10541 CmpVT = MVT::v4i32;
10557 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
10563 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
10567 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
13383 EVT CmpVT = InfoAndKind.IsAArch64
13386 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
13400 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 6440 EVT CmpVT;
6442 CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
6455 CmpVT = VT;
6462 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
6470 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
6472 Merged = DAG.getNOT(dl, Merged, CmpVT);
6477 if (CmpVT.getVectorElementType() == MVT::i64)
6508 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0,
6510 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1,
6512 SDValue Result = DAG.getNode(ISD::OR, dl, CmpVT, TmpOp0, TmpOp1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 7791 EVT CmpVT = Op.getOperand(0).getValueType();
7799 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) {
7801 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT),
7808 if (!CmpVT.isFloatingPoint() || !TV.getValueType().isFloatingPoint() ||
7882 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
7892 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
7898 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
7904 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
7910 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 4691 EVT CmpVT = LHS.getValueType();
4692 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4722 EVT CmpVT = Src0.getValueType();
4725 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeDAG.cpp 3643 EVT CmpVT = Tmp1.getValueType();
3647 EVT CCVT = getSetCCResultType(CmpVT);
SelectionDAGBuilder.cpp 7650 EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits());
7651 LoadL = DAG.getBitcast(CmpVT, LoadL);
7652 LoadR = DAG.getBitcast(CmpVT, LoadR);

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