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    Searched refs:CmpXChg (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AtomicExpandPass.cpp 278 // - into a Cmpxchg/LL-SC loop otherwise
378 case TargetLoweringBase::AtomicExpansionKind::CmpXChg:
474 // This code can go away when cmpxchg supports FP types.
555 case TargetLoweringBase::AtomicExpansionKind::CmpXChg: {
564 TargetLoweringBase::AtomicExpansionKind::CmpXChg);
764 /// It will create an LL/SC or cmpxchg loop, as appropriate, the same
789 if (ExpansionKind == TargetLoweringBase::AtomicExpansionKind::CmpXChg) {
842 // The basic idea here is that we're expanding a cmpxchg of a
843 // smaller memory size up to a word-sized cmpxchg. To do this, we
844 // need to add a retry-loop for strong cmpxchg, so tha
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 255 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
1842 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1888 /// Perform a masked cmpxchg using a target-specific intrinsic. This
1894 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1949 // expansion of a cmpxchg instruction is such that the store-conditional will
1978 /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1989 AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
2296 /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2920 /// Size in bits of the minimum cmpxchg or ll/sc operation th
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 12121 return AtomicExpansionKind::CmpXChg;
12134 return AtomicExpansionKind::CmpXChg;
12138 return AtomicExpansionKind::CmpXChg;
12143 return AtomicExpansionKind::CmpXChg;
12149 return AtomicExpansionKind::CmpXChg;
12152 : AtomicExpansionKind::CmpXChg;
12167 : AtomicExpansionKind::CmpXChg;
12170 return AtomicExpansionKind::CmpXChg;
AMDGPUISelLowering.cpp 4724 return AtomicExpansionKind::CmpXChg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 1095 return AtomicExpansionKind::CmpXChg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 335 return AtomicExpansionKind::CmpXChg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1359 return AtomicExpansionKind::CmpXChg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 16848 return AtomicExpansionKind::CmpXChg;
16854 // Leave 128 bits to LLSC or CmpXChg.
16880 return AtomicExpansionKind::CmpXChg;
16888 // If subtarget has LSE, leave cmpxchg intact for codegen.
16892 // implement cmpxchg without spilling. If the address being exchanged is also
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 19371 return AtomicExpansionKind::CmpXChg;
19379 return AtomicExpansionKind::CmpXChg;
19393 // implement cmpxchg without spilling. If the address being exchanged is also
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 8291 return AtomicExpansionKind::CmpXChg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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