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    Searched refs:Concat (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InterleavedAccess.cpp 239 static constexpr int Concat[] = {
319 Builder.CreateShuffleVector(Temp[2 * i], Temp[2 * i + 1], Concat);
426 reorderSubVector(VT, TransposedMatrix, VecOut, makeArrayRef(Concat, 16),
537 InVec[j * 6 + i], InVec[j * 6 + i + 3], makeArrayRef(Concat, 32));
543 Vec[i] = Builder.CreateShuffleVector(Vec[i], Vec[i + 3], Concat);
X86PartialReduction.cpp 162 Value *Concat = Builder.CreateShuffleVector(MAdd, Zero, ConcatMask);
164 Mul->replaceAllUsesWith(Concat);
X86ISelLowering.cpp 9784 // Try harder to match 256-bit ops by using extract/concat.
9831 // a concat vector. We must adjust the outputs from the partial horizontal
9866 // a concat vector.
11716 // As we're using both sources then we need to concat them together
19888 // Need to concat with zero vector for strict fp to avoid spurious
20291 // Need to concat with zero vector for strict fp to avoid spurious
20774 // Concat upper and lower parts.
20779 // Concat upper and lower parts.
20981 // Recursively pack lower/upper subvectors, concat result and pack again.
21029 // truncate and concat the results. There's an additional complication i
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64LegalizerInfo.cpp 839 auto Concat = MIRBuilder.buildConcatVectors(
843 MI.getOperand(1).setReg(Concat.getReg(0));
AArch64InstructionSelector.cpp 190 // Emit a vector concat operation.
4321 // We implement a vector concat by:
4331 LLVM_DEBUG(dbgs() << "Could not do vector concat of differing vector tys");
4334 assert(Op1Ty.isVector() && "Expected a vector for vector concat");
4337 LLVM_DEBUG(dbgs() << "Vector concat not supported for full size vectors");
4343 LLVM_DEBUG(dbgs() << "Vector concat supported for 64b vectors");
4611 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIB);
4612 if (!Concat) {
4613 LLVM_DEBUG(dbgs() << "Could not do vector concat for tbl1");
4623 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()})
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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp 512 CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts);
514 std::make_pair(Concat, Cand);
522 SubReg2Idx.insert(std::make_pair(Cand, Concat));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 4185 auto Concat = B.buildBuildVector(PackedTy, {VData0, VData1});
4186 MI.getOperand(2).setReg(Concat.getReg(0));
4255 auto Concat = B.buildConcatVectors(PackedAddrTy, PackedRegs);
4256 PackedRegs[0] = Concat.getReg(0);
4470 auto Concat = B.buildConcatVectors(LLT::vector(6, 16), ResultRegs);
4471 B.buildUnmerge({DstReg, MRI->createGenericVirtualRegister(V3S16)}, Concat);
SIISelLowering.cpp 5429 SDValue Concat = InsertLo ?
5433 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
  /src/external/apache2/llvm/dist/llvm/lib/TableGen/
Record.cpp 885 SmallString<80> Concat(I0->getValue());
886 Concat.append(I1->getValue());
887 return StringInit::get(Concat,
964 case CONCAT: {
1155 case CONCAT: Result = "!con"; break;
  /src/external/gpl3/gcc.old/dist/libphobos/src/std/
typecons.d 1477 // tuple concat
1488 // tuple concat
1504 // tuple concat
1513 // tuple concat
1522 // tuple concat
5893 // Concat all Targets function members into one tuple
5894 template Concat(size_t i = 0)
5897 alias Concat = AliasSeq!();
5900 alias Concat = AliasSeq!(OnlyVirtual!(GetOverloadedMethods!(Targets[i]), Concat!(i + 1)))
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeDAG.cpp 4788 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4789 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4910 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4911 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
DAGCombiner.cpp 12188 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
19039 assert(NumConcats >= 2 && "Concat needs at least two inputs!");
19485 // If X is a build_vector itself, the concat can become a larger build_vector.
19497 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N),
19499 return DAG.getBitcast(VT, Concat);
19718 // All operands of the concat must be the same kind of cast from the same
19753 // concat (cast X), (cast Y)... -> cast (concat X, Y...)
19773 assert(In.getValueType().isVector() && "Must concat vectors")
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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineAndOrXor.cpp 2213 /// Attempt to combine or(zext(x),shl(zext(y),bw/2) concat packing patterns.
2249 // BSWAP: Push the concat down, swapping the lower/upper sources.
2250 // concat(bswap(x),bswap(y)) -> bswap(concat(x,y))
2256 // BITREVERSE: Push the concat down, swapping the lower/upper sources.
2257 // concat(bitreverse(x),bitreverse(y)) -> bitreverse(concat(x,y))
2681 if (Instruction *Concat = matchOrConcat(I, Builder))
2682 return replaceInstUsesWith(I, Concat);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 8991 // Example: dup v4i32 (concat v2i32 X, v2i32 Y), 3 --> dup v4i32 Y, 1
9117 if (SDValue Concat = tryFormConcatFromShuffle(Op, DAG))
9118 return Concat;
16345 SDValue Concat =
16347 return DAG.getMergeValues({Concat, Chain}, DL);
16364 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds);
16365 return DAG.getMergeValues({Concat, Chain}, DL);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 1312 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1313 MO.setReg(Concat.getReg(0));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 8428 // shuffle(concat(v1, undef), concat(v2, undef))
8430 // shuffle(concat(v1, v2), undef)
8436 // Look through the concat when lowering them:
8437 // shuffle(concat(v1, v2), undef)
8439 // concat(VZIP(v1, v2):0, :1)
8456 "In-place shuffle of concat can only have one result!");
11972 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT,
11974 Ops.push_back(Concat);
14551 // shuffle(concat(v1, undef), concat(v2, undef)) -
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