| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 26 DefinedSVal Cond,
29 if (Optional<Loc> LV = Cond.getAs<Loc>()) {
38 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>();
41 return assume(State, Cond.castAs<NonLoc>(), Assumption);
45 NonLoc Cond, bool Assumption) {
46 State = assumeAux(State, Cond, Assumption);
48 return EE->processAssume(State, Cond, Assumption);
53 NonLoc Cond,
58 if (!canReasonAbout(Cond)) {
60 SymbolRef Sym = Cond.getAsSymbol()
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Utils/ |
| GuardUtils.h | 38 /// *set* it's condition such that (only) 'Cond' is known to hold on the taken
40 void setWidenableBranchCond(BranchInst *WidenableBR, Value *Cond);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 107 SmallVectorImpl<MachineOperand> &Cond,
125 Cond.push_back(MachineOperand::CreateImm(true));
126 Cond.push_back(MI.getOperand(1));
133 Cond.push_back(MachineOperand::CreateImm(false));
134 Cond.push_back(MI.getOperand(1));
176 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
179 if (Cond.empty()) {
187 assert(Cond.size() == 2 && "Expected a flag and a successor block");
189 if (Cond[0].getImm())
190 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1])
[all...] |
| WebAssemblyLowerBrUnless.cpp | 71 Register Cond = MI->getOperand(1).getReg();
75 if (MFI.isVRegStackified(Cond)) {
76 assert(MRI.hasOneDef(Cond));
77 MachineInstr *Def = MRI.getVRegDef(Cond);
178 Cond = Def->getOperand(1).getReg();
193 .addReg(Cond);
195 Cond = Tmp;
204 .addReg(Cond);
|
| WebAssemblyInstrInfo.h | 58 SmallVectorImpl<MachineOperand> &Cond,
63 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
67 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
| WebAssemblyFixBrTableDefaults.cpp | 97 SmallVector<MachineOperand, 2> Cond;
99 bool Analyzed = !TII.analyzeBranch(*HeaderMBB, TBB, FBB, Cond);
114 assert(Cond.size() == 2 && Cond[1].isReg() && "Unexpected condition info");
123 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg());
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| LibCallsShrinkWrap.cpp | 95 void shrinkWrapCI(CallInst *CI, Value *Cond);
138 Value *Cond = nullptr;
149 Cond = createOrCond(CI, CmpInst::FCMP_OLT, -1.0f, CmpInst::FCMP_OGT, 1.0f);
160 Cond = createOrCond(CI, CmpInst::FCMP_OEQ, INFINITY, CmpInst::FCMP_OEQ,
169 Cond = createCond(CI, CmpInst::FCMP_OLT, 1.0f);
177 Cond = createCond(CI, CmpInst::FCMP_OLT, 0.0f);
183 shrinkWrapCI(CI, Cond);
190 Value *Cond = nullptr;
208 Cond = generateTwoRangeCond(CI, Func);
215 Cond = generateOneRangeCond(CI, Func)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 58 SmallVectorImpl<MachineOperand> &Cond,
63 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
| NVPTXInstrInfo.cpp | 98 SmallVectorImpl<MachineOperand> &Cond,
116 Cond.push_back(LastInst.getOperand(0));
134 Cond.push_back(SecondLastInst.getOperand(0));
183 ArrayRef<MachineOperand> Cond,
190 assert((Cond.size() == 1 || Cond.size() == 0) &&
195 if (Cond.empty()) // Unconditional branch
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
|
| /src/external/apache2/llvm/dist/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| SimpleConstraintManager.h | 39 ProgramStateRef assume(ProgramStateRef State, DefinedSVal Cond,
82 ProgramStateRef assume(ProgramStateRef State, NonLoc Cond, bool Assumption);
84 ProgramStateRef assumeAux(ProgramStateRef State, NonLoc Cond,
|
| ConstraintManager.h | 86 DefinedSVal Cond,
93 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) {
94 ProgramStateRef StTrue = assume(State, Cond, true);
96 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary
100 assert(assume(State, Cond, false) && "System is over constrained.");
105 ProgramStateRef StFalse = assume(State, Cond, false);
129 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 58 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
61 SmallVectorImpl<MachineOperand> &Cond,
67 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
| MSP430InstrInfo.cpp | 132 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
133 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
135 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
159 Cond[0].setImm(CC);
166 SmallVectorImpl<MachineOperand> &Cond,
201 Cond.clear();
225 if (Cond.empty()) {
228 Cond.push_back(MachineOperand::CreateImm(BranchCode));
234 assert(Cond.size() == 1);
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 54 SmallVectorImpl<MachineOperand> &Cond,
58 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
82 SmallVectorImpl<MachineOperand> &Cond) const override;
|
| XCoreInstrInfo.cpp | 192 SmallVectorImpl<MachineOperand> &Cond,
220 Cond.push_back(MachineOperand::CreateImm(BranchCode));
221 Cond.push_back(LastInst->getOperand(0));
241 Cond.push_back(MachineOperand::CreateImm(BranchCode));
242 Cond.push_back(SecondLastInst->getOperand(0));
274 ArrayRef<MachineOperand> Cond,
279 assert((Cond.size() == 2 || Cond.size() == 0) &&
284 if (Cond.empty()) {
289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| GuardUtils.cpp | 66 auto *Cond = BI->getCondition();
67 if (!Cond->hasOneUse())
73 if (match(Cond, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) {
85 if (!match(Cond, m_And(m_Value(A), m_Value(B))))
87 auto *And = dyn_cast<Instruction>(Cond);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFAdjustOpt.cpp | 182 auto *Cond = dyn_cast<ICmpInst>(BI->getCondition());
183 if (!Cond || B2->getFirstNonPHI() != Cond)
185 Value *B2Op0 = Cond->getOperand(0);
186 auto Cond2Op = Cond->getPredicate();
192 Cond = dyn_cast<ICmpInst>(BI->getCondition());
193 if (!Cond)
195 Value *B1Op0 = Cond->getOperand(0);
196 auto Cond1Op = Cond->getPredicate();
211 PassThroughInfo Info(Cond, BI, 0)
[all...] |
| BPFInstrInfo.h | 50 SmallVectorImpl<MachineOperand> &Cond,
56 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsInstrInfo.h | 65 SmallVectorImpl<MachineOperand> &Cond,
72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
81 SmallVectorImpl<MachineOperand> &Cond,
185 SmallVectorImpl<MachineOperand> &Cond) const;
188 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCInstrInfo.h | 55 SmallVectorImpl<MachineOperand> &Cond,
59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
82 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
| ARCInstrInfo.cpp | 173 SmallVectorImpl<MachineOperand> &Cond,
202 if (!Cond.empty())
208 Cond.push_back(I->getOperand(1));
209 Cond.push_back(I->getOperand(2));
210 Cond.push_back(I->getOperand(3));
225 Cond.clear();
351 SmallVectorImpl<MachineOperand> &Cond) const {
352 assert((Cond.size() == 3) && "Invalid ARC branch condition!");
353 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm()))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 69 SmallVectorImpl<MachineOperand> &Cond,
76 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
81 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrInfo.h | 67 SmallVectorImpl<MachineOperand> &Cond,
74 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
79 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| GuardUtils.h | 35 /// %cond = ...
37 /// %branch_cond = and i1 %cond, %wc
39 /// The function returns true, and the values %cond and %wc and blocks
49 bool parseWidenableBranch(User *U, Use *&Cond, Use *&WC, BasicBlock *&IfTrueBB,
|
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| Parallel.cpp | 68 Cond.notify_all();
94 Cond.notify_one();
102 Cond.wait(Lock, [&] { return Stop || !WorkStack.empty(); });
115 std::condition_variable Cond;
|
