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    Searched refs:CondCodes (Results 1 - 25 of 39) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430.h 22 enum CondCodes {
MSP430InstrInfo.cpp 135 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
219 MSP430CC::CondCodes BranchCode =
220 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRInstrInfo.h 31 enum CondCodes {
69 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
70 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
71 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
AVRInstrInfo.cpp 194 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
217 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
240 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
324 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
386 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
421 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
470 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Utils/
ARMBaseInfo.h 28 // The CondCodes constants map directly to the 4-bit encoding of the
30 enum CondCodes { // Meaning (integer) Meaning (floating-point)
48 inline static CondCodes getOppositeCondition(CondCodes CC) {
71 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
146 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2ITBlockPass.cpp 67 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
137 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
187 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
226 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
243 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
ThumbRegisterInfo.h 42 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
Thumb2InstrInfo.h 78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
ARMBaseInstrInfo.h 166 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
168 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
540 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
767 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
783 ARMCC::CondCodes Pred, Register PredReg,
790 ARMCC::CondCodes Pred, Register PredReg,
ARMLoadStoreOptimizer.cpp 173 ARMCC::CondCodes Pred, unsigned PredReg);
177 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
183 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
487 ARMCC::CondCodes Pred,
628 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
835 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
906 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
1189 ARMCC::CondCodes Pred, Register PredReg) {
1221 ARMCC::CondCodes Pred, Register PredReg, int &Offset) {
1241 ARMCC::CondCodes Pred, Register PredReg, int &Offset
    [all...]
ThumbRegisterInfo.cpp 65 ARMCC::CondCodes Pred, unsigned PredReg,
85 ARMCC::CondCodes Pred, unsigned PredReg,
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
ARMInstructionSelector.cpp 54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
391 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
393 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
575 ARMCC::CondCodes Cond,
MLxExpansionPass.cpp 281 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
ARMBaseRegisterInfo.h 189 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
ARMBlockPlacement.cpp 207 MIB.addImm(ARMCC::CondCodes::AL);
Thumb2SizeReduction.cpp 186 bool is2Addr, ARMCC::CondCodes Pred,
333 bool is2Addr, ARMCC::CondCodes Pred,
803 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
896 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
ARMBaseRegisterInfo.cpp 480 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
827 ARMCC::CondCodes Pred = (PIdx == -1)
828 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
MVETPAndVPTOptimisationsPass.cpp 536 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) {
538 return ARMCC::CondCodes(Instr.getOperand(3).getImm());
555 ARMCC::CondCodes ExpectedCode = GetCondCode(Cond);
Thumb2InstrInfo.cpp 74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
279 ARMCC::CondCodes Pred, Register PredReg,
753 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
Sparc.h 40 enum CondCodes {
94 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
SparcInstrInfo.cpp 81 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
300 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm());
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTX.h 27 enum CondCodes {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/
SparcInstPrinter.cpp 200 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/
Target.cpp 921 auto CondCodes = seq((int)X86::CondCode::COND_O,
923 Choices.reserve(std::distance(CondCodes.begin(), CondCodes.end()));
924 for (int CondCode : CondCodes)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMInstPrinter.cpp 962 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
973 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
983 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
991 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();

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