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    Searched refs:CondRegs (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FlagsCopyLowering.cpp 105 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
112 MachineOperand &FlagUse, CondRegArray &CondRegs);
116 CondRegArray &CondRegs);
120 MachineOperand &FlagUse, CondRegArray &CondRegs);
124 CondRegArray &CondRegs);
130 MachineOperand &FlagUse, CondRegArray &CondRegs);
538 CondRegArray CondRegs = collectCondsInRegs(*TestMBB, TestPos);
622 rewriteCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
624 rewriteFCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
626 rewriteSetCC(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 2170 SmallVector<Register, 1> CondRegs(OpdMapper.getVRegs(1));
2171 if (CondRegs.empty())
2172 CondRegs.push_back(MI.getOperand(1).getReg());
2174 assert(CondRegs.size() == 1);
2177 const RegisterBank *CondBank = getRegBank(CondRegs[0], MRI, *TRI);
2185 B.buildZExt(NewCondReg, CondRegs[0]);
2217 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]);
2218 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]);

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