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    Searched refs:Const1 (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 940 SDValue Const1;
943 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
944 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
2321 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2330 Const1);
2334 Const1);
2339 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2340 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2347 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2348 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 2759 SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);
2760 SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1});
2763 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1});
2764 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1});
2817 SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);
2818 SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1});
2821 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1});
2822 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1});
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 7879 bool Const1 = isa<ConstantInt>(Op1) || isa<ConstantFP>(Op1) ||
7881 if (Const0 || Const1) {
7882 if (!Const0 || !Const1) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 1964 auto Const1 = B.buildConstant(S32, ExpBits);
1969 .addUse(Const1.getReg(0));

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