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    Searched refs:CopyOpc (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ThumbRegisterInfo.cpp 196 int CopyOpc = 0;
209 // * CopyOpc - DestReg = BaseReg + imm
224 CopyOpc = ARM::tMOVr;
234 CopyOpc = ARM::tADDrSPi;
242 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
247 CopyOpc = ARM::tMOVr;
259 CopyOpc = ARM::tMOVr;
272 if (CopyOpc && Bytes < CopyScale) {
273 CopyOpc = ARM::tMOVr;
279 unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyCFGStackify.cpp 855 unsigned CopyOpc = getCopyOpcode(MRI.getRegClass(DefReg));
856 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), TeeReg)
858 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), Reg).addReg(DefReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 3725 static bool getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg,
3731 CopyOpc = AArch64::CPYi16;
3735 CopyOpc = AArch64::CPYi32;
3739 CopyOpc = AArch64::CPYi64;
3754 unsigned CopyOpc = 0;
3756 if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, ScalarTy.getSizeInBits())) {
3802 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx);
3909 unsigned CopyOpc = 0;
3911 if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, NarrowTy.getSizeInBits()))
3968 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CopyOpc), CopyTo
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp 2513 unsigned CopyOpc = TargetOpcode::COPY;
2515 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2517 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2518 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)

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