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    Searched refs:Cycle (Results 1 - 19 of 19) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ModuloSchedule.h 18 // A schedule is, for every instruction in a block, a Cycle and a Stage. Note
22 // The Cycle of an instruction defines a partial order of the instructions in
23 // the remapped loop. Instructions within a cycle must not consume the output
24 // of any instruction in the same cycle. Cycle information is assumed to have
77 /// maintain a Cycle and Stage.
83 /// The instructions to be generated, in total order. Cycle provides a partial
88 /// The cycle for each instruction.
89 DenseMap<MachineInstr *, int> Cycle;
101 /// \arg Cycle Cycle index for all instructions in ScheduledInstrs. Cycle doe
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MachineTraceMetrics.h 77 unsigned Cycle = 0;
239 /// InstrCycles represents the cycle height and depth of an instruction in a
242 /// Earliest issue cycle as determined by data dependencies and instruction
413 // Convert scaled resource usage to a cycle count that can be compared with
ScheduleDAG.h 299 unsigned TopReadyCycle = 0; ///< Cycle relative to start when node is ready.
300 unsigned BotReadyCycle = 0; ///< Cycle relative to end when node is ready.
546 void setCurCycle(unsigned Cycle) {
547 CurCycle = Cycle;
750 /// Returns true if addPred(TargetSU, SU) creates a cycle.
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineTraceMetrics.cpp 580 // need to erase the Cycle entries. They will be overwritten when we
619 // and instruction latencies. These cycle numbers assume that the CPU can issue
620 // an infinite number of instructions per cycle as long as their dependencies
791 // Filter and process dependencies, computing the earliest issue cycle.
792 unsigned Cycle = 0;
805 Cycle = std::max(Cycle, DepCycle);
809 MICycles.Depth = Cycle;
813 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height);
814 LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI)
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ModuloSchedule.cpp 1397 // In addition, Consumer's cycle must be scheduled after Producer in the
1436 // (because the producer is scheduled at an earlier cycle than the consumer)
2096 // "Stage=%d Cycle=%d".
2139 static void parseSymbolString(StringRef S, int &Cycle, int &Stage) {
2153 CycleTokenAndValue.second.drop_front().getAsInteger(10, Cycle);
2155 dbgs() << " Stage=" << Stage << ", Cycle=" << Cycle << "\n";
2163 DenseMap<MachineInstr *, int> Cycle, Stage;
2171 parseSymbolString(Sym->getName(), Cycle[&MI], Stage[&MI]);
2175 ModuloSchedule MS(MF, &L, std::move(Instrs), std::move(Cycle),
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MachinePipeliner.cpp 614 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle();
615 ++Cycle) {
616 for (SUnit *SU : Schedule.getInstructions(Cycle)) {
618 Cycles[SU->getInstr()] = Cycle;
1092 /// for each cycle that is required. When adding a new instruction, we attempt
1123 // DFA is needed for each cycle.
1416 // Add the artificial dependencies if it does not form a cycle.
2073 // When scheduling a Phi it is better to start at the late cycle and go
2378 // Add the already scheduled instructions at the specified cycle to th
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IfConversion.cpp 130 /// ExtraCost - Extra cost for multi-cycle instructions.
287 unsigned Cycle, unsigned Extra,
289 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
  /src/external/apache2/llvm/dist/clang/include/clang/AST/
ASTImporter.h 145 // Now what happens if there is a cycle in the import path?
170 // Such situation can happen only if during the visitation we had a cycle.
171 // If we didn't have any cycle, then the normal way of passing an Error
197 using Cycle = llvm::iterator_range<VecTy::const_reverse_iterator>;
198 Cycle getCycleAtBack() const {
200 return Cycle(Nodes.rbegin(),
205 /// Returns the copy of the cycle.
214 // Auxiliary container to be able to answer "Do we have a cycle ending
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
Instruction.h 214 // On every cycle, update CyclesLeft and notify dependent users.
299 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; }
486 // cycle because of unavailable pipeline resources.
520 // of a new cycle (see method cycleEvent()), or as a result of another issue
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
RegisterFile.h 62 void notifyExecuted(unsigned Cycle);
92 // moves eliminated per cycle.
103 // cycle. A value of zero means that there is no limit in the number of
104 // moves which can be eliminated every cycle.
107 // Number of register moves eliminated during this cycle.
110 // Every new cycle, this value is reset to zero.
288 // Notify each PRF that a new cycle just started.
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonLoopIdiomRecognition.cpp 598 bool findCycle(Value *Out, Value *In, ValueSeq &Cycle);
599 void classifyCycle(Instruction *DivI, ValueSeq &Cycle, ValueSeq &Early,
1134 ValueSeq &Cycle) {
1149 // The cycle p1->p2->p1 would span two loop iterations.
1150 // Check that there is only one phi in the cycle.
1155 if (Cycle.count(I))
1157 Cycle.insert(I);
1158 if (findCycle(I, In, Cycle))
1160 Cycle.remove(I);
1162 return !Cycle.empty()
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.cpp 424 // only be fetched during the first cycle.
439 unsigned Cycle = getTransSwizzle(TransSwz, i);
444 if (Vector[Src.second][Cycle] < 0)
445 Vector[Src.second][Cycle] = Src.first;
446 if (Vector[Src.second][Cycle] != Src.first)
489 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
490 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
500 unsigned Cycle = getTransSwizzle(TransSwz, i);
503 if (ConstCount > 0 && Cycle == 0)
505 if (ConstCount > 1 && Cycle == 1
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  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 36 void WriteRef::notifyExecuted(unsigned Cycle) {
38 WriteBackCycle = Cycle;
416 // Early exit if the PRF cannot eliminate more moves/xchg in this cycle.
  /src/sys/external/bsd/acpica/dist/tools/examples/
extables.c 336 [0001] Duty Cycle Offset : 00
337 [0001] Duty Cycle Width : 00
  /src/external/gpl3/gcc.old/dist/libphobos/src/std/range/
package.d 65 $(TR $(TD $(LREF cycle))
1321 auto inf = chain([0,1,2][], cycle([4,5,6][]), [7,8,9][]); // infinite range
1911 import std.range : cycle;
1912 auto s = chooseAmong(0, cycle(arr2), cycle(arr3));
2563 assert(iota(4).cycle.take(4)[start .. stop]
2591 alias R2 = typeof(cycle([1]));
3871 infinite (fact that would make `Cycle` the identity application),
3872 `Cycle` detects that and aliases itself to the range type
3874 If the original range has random access, `Cycle` offer
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  /src/external/gpl3/gdb/dist/readline/readline/doc/
texi2dvi 171 Every compilation therefore requires the full cycle.
1131 # time. This will mean that if they don't change, we finish in 1 cycle.
1144 verbose "Cycle $suite_cycle for $command_line_filename"
1679 # Called at the end of each compilation cycle, and at the end of
  /src/external/gpl3/gdb.old/dist/readline/readline/doc/
texi2dvi 171 Every compilation therefore requires the full cycle.
1131 # time. This will mean that if they don't change, we finish in 1 cycle.
1144 verbose "Cycle $suite_cycle for $command_line_filename"
1679 # Called at the end of each compilation cycle, and at the end of
  /src/distrib/syspkg/mk/
bsd.syspkg.mk 408 ${SHCOMMENT} Cycle through some FTP server here ;\
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 146 // to use the listed output operand cycle number (using operand 0 here, which
156 int Cycle = ItinData->getOperandCycle(DefClass, i);
157 if (Cycle < 0)
160 Latency = std::max(Latency, (unsigned) Cycle);
1559 // an open question. On the A2, the isel instruction has a 2-cycle latency
1560 // but single-cycle throughput. These numbers are used in combination with

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