| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86PadShortFunction.cpp | 42 // Cycles - Number of cycles until return if HasReturn is true, otherwise
43 // number of cycles until end of the BB
44 unsigned int Cycles;
46 VisitedBBInfo() : HasReturn(false), Cycles(0) {}
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles)
48 : HasReturn(HasReturn), Cycles(Cycles) {}
76 unsigned int Cycles = 0);
79 unsigned int &Cycles);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| Instruction.cpp | 22 unsigned Cycles) {
25 CRD.Cycles = Cycles;
26 DependentWriteCyclesLeft = Cycles;
31 unsigned Cycles) {
41 if (TotalCycles < Cycles) {
44 CRD.Cycles = Cycles;
45 TotalCycles = Cycles;
56 // Update the number of cycles left based on the WriteDescriptor info
[all...] |
| Pipeline.cpp | 45 ++Cycles;
48 return Cycles;
86 LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n');
92 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n");
|
| InstrBuilder.cpp | 48 // Track cycles contributed by resources that are in a "Super" relationship.
51 // of "consumed" processor resources and resource cycles, the logic in
52 // ExpandProcResource() doesn't update the number of resource cycles
56 // This map stores the number of cycles contributed by sub-resources that are
68 if (!PRE->Cycles) {
71 << "Ignoring invalid write of zero cycles on processor resource "
88 CycleSegment RCy(0, PRE->Cycles, false);
92 SuperResources[Super] += PRE->Cycles;
113 // Remove cycles contributed by smaller resources.
142 // A SchedWrite may specify a number of cycles in which a resource grou
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| Pipeline.h | 43 /// The Pipeline entry point is method 'run()' which executes cycles in a loop
57 unsigned Cycles;
65 Pipeline() : Cycles(0) {}
68 /// Returns the total number of simulated cycles.
|
| Support.h | 44 /// This class represents the number of cycles per resource (fractions of
45 /// cycles). That quantity is managed here as a ratio, and accessed via the
46 /// double cast-operator below. The two quantities, number of cycles and
48 /// ResourcePressureView to calculate the average resource cycles
55 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
56 : Numerator(Cycles), Denominator(ResourceUnits) {}
105 /// cycles. The reciprocal block throughput is computed as the MAX between:
|
| Instruction.h | 42 // Write latency. Number of cycles before write-back stage.
90 unsigned Cycles;
97 /// register write. It also tracks how many cycles are left before the write
103 // value that represents an "unknown" number of cycles.
146 // The 'second' element of a pair is a "ReadAdvance" number of cycles.
173 // number of cycles to subtract from the latency of this data dependency.
204 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
223 /// Tracks register operand latency in cycles.
237 // Number of cycles left before RegisterID can be read. This value depends on
276 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCSchedule.h | 45 // fixed number of cycles after dispatch. If a resource is unbuffered, then
63 /// scheduling class for the specified number of cycles.
66 uint16_t Cycles;
69 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
73 /// Specify the latency in cpu cycles for a particular scheduling class and def
79 int16_t Cycles;
83 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
87 /// Specify the number of cycles allowed after instruction issue before
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| InstructionTables.cpp | 32 unsigned Cycles = Resource.second.size();
37 // The number of cycles consumed by each unit.
41 std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits)));
48 // Uniformly distribute Cycles across all of the units.
52 // Compute the number of cycles consumed by each resource unit.
56 ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits)));
|
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCSchedule.cpp | 49 if (WLEntry->Cycles < 0)
50 return WLEntry->Cycles;
51 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
95 if (!I->Cycles)
98 double Temp = NumUnits * 1.0 / I->Cycles;
163 DelayCycles = std::min(DelayCycles, E.Cycles);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/ |
| LSUnit.h | 122 unsigned Cycles = IR.getInstruction()->getCyclesLeft();
123 if (CriticalPredecessor.Cycles < Cycles) {
125 CriticalPredecessor.Cycles = Cycles;
187 if (isWaiting() && CriticalPredecessor.Cycles)
188 CriticalPredecessor.Cycles--;
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| TimelineView.cpp | 22 unsigned Cycles)
24 MaxCycle(Cycles == 0 ? 80 : Cycles), LastCycle(0), WaitTime(S.size()),
97 // expanded into multiple uOps may require multiple dispatch cycles. Here,
121 static void tryChangeColor(raw_ostream &OS, unsigned Cycles,
126 raw_ostream::Colors Color = chooseColor(Cycles, Executions, BufferSize);
256 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) {
258 if (Cycles >= 10) {
260 for (unsigned I = 0; I <= Cycles; ++I) {
271 for (unsigned I = 0; I <= Cycles; ++I)
[all...] |
| TimelineView.h | 53 /// dots ('.') and empty spaces are cycles where the instruction is not
63 /// wait for two cycles before being issued. That is because operands
69 /// To better understand why instructions had to wait for multiple cycles in
90 /// cycles were spent in the scheduler's queue due to data dependencies.
92 /// In this example, instruction 5 spent an average of ~6 cycles in the
167 unsigned Cycles);
|
| BottleneckAnalysis.cpp | 215 // latency as well as the actual delay (in cycles) caused to users.
507 unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID);
514 addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles);
520 if (RegDep.Cycles) {
521 Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID);
523 addRegisterDep(From, To, RegDep.RegID, Cycles);
527 if (MemDep.Cycles) {
528 Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| SchedClassResolution.cpp | 24 // entries. Each entry describe how many cycles are spent on a specific ProcRes
30 // P016 (ProcResIdx=10), then the cycles consumed by P0 are also consumed by
32 // by P06 are also consumed by P016. In the figure below, parenthesized cycles
42 // {ProcResIdx=1, Cycles=1} // P0
43 // {ProcResIdx=7, Cycles=3} // P06
44 // {ProcResIdx=10, Cycles=3} // P016
46 // Note that in this case, P016 does not contribute any cycles, so it would
66 Result.push_back({WPR->ProcResourceIdx, WPR->Cycles});
67 ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles;
69 // This is a ProcResGroup. First see if it contributes any cycles or i
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| EarlyIfConversion.cpp | 846 // Adjust cycles with downward saturation.
855 struct Cycles {
859 template <typename Remark> Remark &operator<<(Remark &R, Cycles C) {
860 return R << ore::NV(C.Key, C.Value) << (C.Value == 1 ? " cycle" : " cycles");
902 << Cycles{"ResLength", ResLength}
904 << Cycles{"MinCrit", MinCrit} << ") by more than the threshold of "
905 << Cycles{"CritLimit", CritLimit}
924 unsigned Extra; // Count of extra cycles that the component adds.
925 unsigned Depth; // Absolute depth of the component in cycles.
941 LLVM_DEBUG(dbgs() << "Condition adds " << Extra << " cycles.\n")
[all...] |
| TargetSchedule.cpp | 126 static unsigned capLatency(int Cycles) {
127 return Cycles >= 0 ? Cycles : 1000;
224 unsigned Latency = capLatency(WLEntry->Cycles);
|
| MachineTraceMetrics.cpp | 108 // Add up per-processor resource cycles as well.
130 PRCycles[PI->ProcResourceIdx] += PI->Cycles;
135 // Scale the resource cycles so they are comparable.
339 // Ignore cycles that aren't natural loops.
369 // Ignore cycles that aren't natural loops.
469 // To is a new block. Mark the block as visited in case the CFG has cycles
583 Cycles.erase(&I);
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
800 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
808 InstrCycles &MICycles = Cycles[&UseMI]
[all...] |
| MachineScheduler.cpp | 1322 /// The cyclic critical path is a two cycles: b->c->b
1323 /// The acyclic critical path is four cycles: a->b->c->d->exit
2009 // Track the maximum number of stall cycles that could arise either from the
2010 // latency of a DAG edge or the number of cycles that a processor resource is
2034 RemainingCounts[PIdx] += (Factor * PI->Cycles);
2067 /// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
2068 /// these "soft stalls" differently than the hard stall cycles based on CPU
2087 unsigned Cycles) {
2092 // For bottom-up scheduling add the cycles needed for the current operation.
2094 NextUnreserved += Cycles;
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| SubtargetEmitter.cpp | 111 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
307 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
308 int Cycles = Stage->getValueAsInt("Cycles");
309 ItinString += " { " + itostr(Cycles) + ", ";
336 // number of operands that has cycles specified.
434 // operand cycles, and pipeline bypass tables. Then add the new Itinerary
483 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
535 // Closing operand cycles
536 OperandCycleTable += " 0 // End operand cycles\n"
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZHazardRecognizer.cpp | 190 if (PI->Cycles > 1)
191 OS << "(" << PI->Cycles << "cyc)";
304 CurrCounter += PI->Cycles;
404 Cost = PI->Cycles;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 35 // cycles required to execute the trace when execution is limited by data
37 // of cycles required to execute all instructions in the trace when ignoring
40 // Every instruction in the current block has a slack - the number of cycles
132 /// Get the scaled number of cycles used per processor resource in MBB.
225 /// Critical path length. This is the number of cycles in the longest data
247 /// Minimum number of cycles from this instruction is issued to the of the
272 /// This is the number of cycles required to execute all instructions from
278 /// Return the resource length of the trace. This is the number of cycles
299 return TE.Cycles.lookup(&MI);
302 /// Return the slack of MI. This is the number of cycles MI can be delaye
[all...] |
| MachineScheduler.h | 631 /// Number of cycles it takes to issue the instructions scheduled in this
706 /// Number of cycles to issue the instructions scheduled in this zone.
715 /// Get the number of latency cycles "covered" by the scheduled
717 /// and the number of cycles required to issue the instructions.
756 unsigned Cycles);
760 unsigned Cycles);
789 unsigned Cycles, unsigned ReadyCycle);
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/ |
| llvm-mca.cpp | 176 "timeline-max-cycles",
178 "Maximum number of cycles in the timeline view. Defaults to 80 cycles"),
291 Expected<unsigned> Cycles = P.run();
292 if (!Cycles) {
293 WithColor::error() << toString(Cycles.takeError());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 383 unsigned Cycles[3] = { 2, 1, 0};
384 return Cycles[Op];
387 unsigned Cycles[3] = { 1, 2, 2};
388 return Cycles[Op];
391 unsigned Cycles[3] = { 2, 1, 2};
392 return Cycles[Op];
395 unsigned Cycles[3] = { 2, 2, 1};
396 return Cycles[Op];
|
