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    Searched refs:D3VGA_CONTROL (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_hwseq.h 209 SR(D3VGA_CONTROL), \
274 SR(D3VGA_CONTROL), \
325 SR(D3VGA_CONTROL), \
417 uint32_t D3VGA_CONTROL;
572 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 515 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
524 REG_WRITE(D3VGA_CONTROL, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 257 REG_WRITE(D3VGA_CONTROL, 0);

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