| /src/sys/arch/m68k/include/ |
| reg.h | 74 #define D6 (6)
|
| /src/external/bsd/pcc/dist/pcc/arch/m68k/ |
| macdefs.h | 143 #define D6 6
210 { D5, D6, D4D5, D6D7, -1}, \
211 { D6, D7, D5D6, -1}, \
|
| /src/external/bsd/pcc/dist/pcc/arch/sparc64/ |
| macdefs.h | 191 #define D6 68
243 { D6, -1 }, { D6, -1 }, { D7, -1 }, { D7, -1 }, \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
| M68kBaseInfo.h | 221 return M68k::D6;
|
| /src/lib/libm/ld128/ |
| s_expl.c | 176 D6 = 1.38888888888888888888887138722762072e-3L,
249 q = x * x2 * D3 + x2 * x2 * (D4 + x * (D5 + x * (D6 +
|
| /src/sys/arch/m68k/m68k/ |
| sig_machdep.c | 209 gr[_REG_D6] = frame->f_regs[D6];
349 frame->f_regs[D6] = gr[_REG_D6];
|
| m68k_machdep.c | 687 tf->tf_regs[D6] = 0;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.cpp | 34 AArch64::D6, AArch64::D7};
|
| AArch64PBQPRegAlloc.cpp | 115 case AArch64::D6:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 80 case D7: case D6: case D5: case D4:
|
| ARMCallingConv.cpp | 160 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 49 MAP(D6, 86) \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 117 case AArch64::D6: return AArch64::B6;
157 case AArch64::B6: return AArch64::D6;
|
| /src/external/gpl3/gdb/dist/gdb/stubs/ |
| m68k-stub.c | 146 enum regnames {D0,D1,D2,D3,D4,D5,D6,D7,
|
| /src/external/gpl3/gdb.old/dist/gdb/stubs/ |
| m68k-stub.c | 146 enum regnames {D0,D1,D2,D3,D4,D5,D6,D7,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 75 D0, D1, D2, D3, D4, D5, D6, D7, 0
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/AsmParser/ |
| M68kAsmParser.cpp | 401 case M68k::D6:
492 M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 173 {codeview::RegisterId::ARM64_D6, AArch64::D6},
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 280 {codeview::RegisterId::ARM_ND6, ARM::D6},
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| M68kDisassembler.cpp | 141 M68k::D4, M68k::D5, M68k::D6, M68k::D7,
|
| /src/sys/arch/mac68k/obio/ |
| iwm.s | 735 moveq #0,%d6
770 addxb %d2,%d6
778 eorb %d6,%d1
835 addxb %d2,%d6
845 eorb %d6,%d1
854 * maintained in %D5/%D6/%D7 for the 1st/2nd/3rd data byte of
884 cmpb %d2,%d6 | Compare second checksum to %D6
1094 moveq #0,%d6
1124 eorb %d6,%d
[all...] |
| /src/sys/arch/m68k/060sp/dist/ |
| isp.s | 294 set EXC_D6, EXC_DREGS+(6*4) # offset of d6
2119 mov.l (EXC_DREGS,%a6,%d1.w*4), %d6 # get dividend lo
2140 negx.l %d6 # complement signed dividend
2150 tst.l %d6 # is (lo(dividend) == 0), too
2153 cmp.l %d7,%d6 # is (divisor <= lo(dividend))
2156 exg %d5,%d6 # q = 0, r = dividend
2160 tdivu.l %d7, %d5:%d6 # it's only a 32/32 bit div!
2189 cmpi.l %d6, &0x80000000 # will (-quot) fit in 32 bits?
2192 neg.l %d6 # make (-quot) 2's comp
2197 btst &0x1f, %d6 # will (+quot) fit in 32 bits
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 593 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 84 SP::D6, SP::D22, SP::D7, SP::D23,
|
| /src/external/apache2/mDNSResponder/dist/mDNSShared/ |
| CommonServices.h | 1433 #define HEX_DIGIT_11010110 D6
|
