| /src/sys/arch/m68k/include/ |
| reg.h | 48 int r_regs[16]; /* D0-D7/A0-A7 */
75 #define D7 (7)
|
| /src/external/bsd/pcc/dist/pcc/arch/sparc64/ |
| macdefs.h | 192 #define D7 69
243 { D6, -1 }, { D6, -1 }, { D7, -1 }, { D7, -1 }, \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
| M68kBaseInfo.h | 223 return M68k::D7;
|
| /src/external/bsd/pcc/dist/pcc/arch/m68k/ |
| macdefs.h | 144 #define D7 7
211 { D6, D7, D5D6, -1}, \
|
| /src/lib/libm/ld128/ |
| s_expl.c | 177 D7 = 1.98412698412698412699085805424661471e-4L,
250 x * (D7 + x * (D8 + x * (D9 + x * (D10 +
|
| /src/sys/arch/m68k/m68k/ |
| sig_machdep.c | 210 gr[_REG_D7] = frame->f_regs[D7];
350 frame->f_regs[D7] = gr[_REG_D7];
|
| m68k_machdep.c | 688 tf->tf_regs[D7] = 0;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.cpp | 34 AArch64::D6, AArch64::D7};
|
| AArch64PBQPRegAlloc.cpp | 66 case AArch64::D7:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 80 case D7: case D6: case D5: case D4:
|
| ARMCallingConv.cpp | 160 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 50 MAP(D7, 87) \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 118 case AArch64::D7: return AArch64::B7;
158 case AArch64::B7: return AArch64::D7;
|
| /src/external/gpl3/gdb/dist/gdb/stubs/ |
| m68k-stub.c | 146 enum regnames {D0,D1,D2,D3,D4,D5,D6,D7,
269 asm(" moveml _registers,d0-d7/a0-a6");
325 moveml d0-d7/a0-a6,_registers /* save registers */
411 moveml d0-d7/a0-a6,_registers /* save registers */
|
| /src/external/gpl3/gdb.old/dist/gdb/stubs/ |
| m68k-stub.c | 146 enum regnames {D0,D1,D2,D3,D4,D5,D6,D7,
269 asm(" moveml _registers,d0-d7/a0-a6");
325 moveml d0-d7/a0-a6,_registers /* save registers */
411 moveml d0-d7/a0-a6,_registers /* save registers */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 75 D0, D1, D2, D3, D4, D5, D6, D7, 0
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/AsmParser/ |
| M68kAsmParser.cpp | 402 case M68k::D7:
492 M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 174 {codeview::RegisterId::ARM64_D7, AArch64::D7},
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 281 {codeview::RegisterId::ARM_ND7, ARM::D7},
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| M68kDisassembler.cpp | 141 M68k::D4, M68k::D5, M68k::D6, M68k::D7,
|
| /src/sys/arch/m68k/060sp/dist/ |
| isp.s | 293 set EXC_D7, EXC_DREGS+(7*4) # offset of d7
411 movm.l &0x3fff,EXC_DREGS(%a6) # store d0-d7/a0-a5
598 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
664 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
698 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
735 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
773 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
800 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
820 movm.l (%sp)+,&0x7fff # restore d0-d7/a0-a6
839 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 593 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 84 SP::D6, SP::D22, SP::D7, SP::D23,
|
| /src/external/apache2/mDNSResponder/dist/mDNSShared/ |
| CommonServices.h | 1434 #define HEX_DIGIT_11010111 D7
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 1175 VA.convertToReg(Mips::D7);
1334 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
|
