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    Searched refs:DCC (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/arch/ews4800mips/include/
sbd_tr2.h 138 /* DCC (DMA controller. Parallel port and FDD use this.) */
139 struct DCC {
147 #define FDC_DMA ((volatile struct DCC *)0xbb030000)
152 #define LPT_DMA (((volatile struct DCC *)0xbb040000)
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
vexpress-v2p-ca5s.dts 143 dcc {
201 temp-dcc {
202 /* DCC internal operating temperature */
205 label = "DCC";
vexpress-v2p-ca15-tc1.dts 141 dcc {
217 temp-dcc {
218 /* DCC internal temperature */
221 label = "DCC";
vexpress-v2p-ca15_a7.dts 252 dcc {
373 temp-dcc {
374 /* DCC internal temperature */
377 label = "DCC";
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_gem_fence_reg.c 677 u32 dcc = intel_uncore_read(uncore, DCC); local in function:detect_bit_6_swizzle
681 * determined by DCC. For single-channel, neither the CPU
688 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
695 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
702 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
721 if (dcc == 0xffffffff) {
i915_debugfs.c 1581 intel_uncore_read(uncore, DCC));
i915_reg.h 3707 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
  /src/sys/external/bsd/drm/dist/shared-core/
i915_reg.h 523 #define DCC 0x10200

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