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    Searched refs:DCFE_MEM_PWR_CTRL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_ipp.c 184 if (REG(DCFE_MEM_PWR_CTRL))
185 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
216 if (REG(DCFE_MEM_PWR_CTRL))
217 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
dce_ipp.h 60 SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
64 SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
110 IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
215 uint32_t DCFE_MEM_PWR_CTRL;
amdgpu_dce_transform.c 202 if (REG(DCFE_MEM_PWR_CTRL)) {
203 power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);
204 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
236 if (REG(DCFE_MEM_PWR_CTRL))
237 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
1152 if (REG(DCFE_MEM_PWR_CTRL))
1153 REG_UPDATE(DCFE_MEM_PWR_CTRL,
1206 if (REG(DCFE_MEM_PWR_CTRL))
1207 REG_UPDATE(DCFE_MEM_PWR_CTRL,
1310 if (REG(DCFE_MEM_PWR_CTRL))
    [all...]
dce_transform.h 105 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
110 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
202 XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
204 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
205 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
434 uint32_t DCFE_MEM_PWR_CTRL;

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