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    Searched refs:DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_10_0_enum.h 336 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
dce_11_0_enum.h 1105 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
dce_11_2_enum.h 1504 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
vega10_enum.h 12068 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,

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