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Searched refs:DCR_L2C0_SR (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/powerpc/ibm4xx/
ibm4xx_460ex_l2.c	`88 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0) 118 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0) 184 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0) 188 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0) 191 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)`
/src/sys/arch/powerpc/include/ibm4xx/
amcc460ex.h	`180 #define DCR_L2C0_SR 0x034 /* L2 cache status */`

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