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    Searched refs:DCR_MAL0_TXEOBISR (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/powerpc/ibm4xx/dev/
mal.c 145 while ((tcei = mfdcr(DCR_MAL0_TXEOBISR))) {
148 mtdcr(DCR_MAL0_TXEOBISR, MAL0__XCAR_CHAN(chan));
  /src/sys/arch/powerpc/include/ibm4xx/
dcr4xx.h 211 #define DCR_MAL0_TXEOBISR 0x186 /* Tx End of Buffer Interrupt Status Register */

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