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Searched refs:DCR_SDRAM0_CFGADDR (Results 1 - 3 of 3) sorted by relevancy

/src/sys/arch/powerpc/ibm4xx/dev/
ecc_plb.c	`149 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 152 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR); 157 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 231 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 234 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 269 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);`
/src/sys/arch/evbppc/dht/
machdep.c	`147 mtdcr(DCR_SDRAM0_CFGADDR, addr);`
/src/sys/arch/powerpc/include/ibm4xx/
dcr4xx.h	`48 #define DCR_SDRAM0_CFGADDR 0x010 /* Memory Controller Address Register */`

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