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    Searched refs:DC_IP_REQUEST_CNTL (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_hwseq.h 212 SR(DC_IP_REQUEST_CNTL), \
278 SR(DC_IP_REQUEST_CNTL), \
329 SR(DC_IP_REQUEST_CNTL), \
361 uint32_t DC_IP_REQUEST_CNTL;
569 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
635 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
676 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 647 if (REG(DC_IP_REQUEST_CNTL)) {
648 REG_SET(DC_IP_REQUEST_CNTL, 0,
652 REG_SET(DC_IP_REQUEST_CNTL, 0,
669 REG_SET(DC_IP_REQUEST_CNTL, 0,
673 REG_SET(DC_IP_REQUEST_CNTL, 0,
698 REG_SET(DC_IP_REQUEST_CNTL, 0,
702 REG_SET(DC_IP_REQUEST_CNTL, 0,
1067 if (REG(DC_IP_REQUEST_CNTL)) {
1068 REG_SET(DC_IP_REQUEST_CNTL, 0,
1073 REG_SET(DC_IP_REQUEST_CNTL, 0
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 346 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
348 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
405 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
1009 if (REG(DC_IP_REQUEST_CNTL)) {
1010 REG_SET(DC_IP_REQUEST_CNTL, 0,
1014 REG_SET(DC_IP_REQUEST_CNTL, 0,

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