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Searched refs:DDR_BASE (Results 1 - 3 of 3) sorted by relevancy

/src/sys/arch/arm/broadcom/
bcm53xx_board.c	`153 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 154 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 155 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 156 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 405 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 407 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS);`
bcm53xx_ccb.c	`115 { "bcmddr", DDR_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_DDR_CONTROLLER } },`
bcm53xx_reg.h	`127 #define DDR_BASE 0x010000`

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