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    Searched refs:DD_CSR (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/arch/next68k/dev/
nextdmareg.h 58 int dd_csr; /* control & status register */
73 #define DD_CSR 0
74 #define DD_SAVED_NEXT (DD_CSR + sizeof(int) + 0x3fec)
86 * bits in dd_csr
nextdma.c 285 nd_bsw4(DD_CSR, DMACSR_RESET | DMACSR_CLRCOMPLETE);
286 nd_bsw4(DD_CSR, 0);
296 state = nd_bsr4 (DD_CSR);
331 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET);
584 state = nd_bsr4(DD_CSR);
728 printf("CLNDMAP: dd->dd_csr = %s\n", sbuf);
745 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | dmadir);
748 nd_bsw4(DD_CSR,
754 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET);
876 nd_bsw4(DD_CSR, (turbo
899 u_long dd_csr; local in function:nextdma_print
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esp.c 543 (nd_bsr4(DD_CSR) & 0x08000000) == 0 &&
1468 state = nd_bsr4(DD_CSR);
1528 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE |
1548 state = nd_bsr4(DD_CSR);
1555 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE |
1577 nd_bsw4(DD_CSR, DMACSR_SETENABLE | DMACSR_CLRCOMPLETE |
1609 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET);
1611 nd_bsw4(DD_CSR, 0);
1615 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE |
1640 nd_bsw4(DD_CSR, DMACSR_SETENABLE
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