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    Searched refs:DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS (Results 1 - 2 of 2) sorted by relevancy

  /src/external/gpl3/gcc/dist/gcc/config/riscv/
riscv-vector-builtins-types.def 233 /* Use "DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS" macro include all types for
236 #ifndef DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS
237 #define DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
910 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool1_t, 0)
911 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool2_t, 0)
912 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool4_t, 0)
913 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool8_t, 0)
914 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool16_t, 0)
915 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool32_t, 0)
916 DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64
    [all...]
riscv-vector-builtins.cc 420 #define DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \

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