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    Searched refs:DENORM_CONTROL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_mpc.h 81 SRII(DENORM_CONTROL, MPC_OUT, inst),\
134 uint32_t DENORM_CONTROL[MAX_OPP]; \
amdgpu_dcn20_mpc.c 113 REG_UPDATE(DENORM_CONTROL[opp_id],
124 REG_UPDATE_2(DENORM_CONTROL[opp_id],
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_transform.h 72 SRI(DENORM_CONTROL, DCP, id), \
130 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
420 uint32_t DENORM_CONTROL;
amdgpu_dce_transform.c 749 REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);

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